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Re: [f-cpu] Conditionnal Load and Store



Quoting Michael Riepe <michael@stud.uni-hannover.de>:

> On Fri, Jul 26, 2002 at 03:18:15PM +0200, Cedric BAIL wrote:
> > Why didn't we have conditionnal load and store. I mean somtehing like
> > storez, storenz, loadz, loadnz, ... It can be really usefull and we can do
> > with that all what we can do with predicate I think.

> Conditional load/store makes less sense than you may think. When an
> address is loaded into a register, the prefetch cycle begins, whether
> or not memory is actually accessed. Thus, there will be no increase in
> memory bandwidth due to the use of conditional load/store.

Arf, I forgot prefetch... A conditional prefetch, is it possible ? ;-D

That not so stupid in fact. We have our strange cachemm instruction (I
mean what did you think about : cachemmlcV, it's fun but have no sense...)
So why not changing it, so that we have a conditionnal cachemm. In that case
we need 2 more bits to define a register and 3 more for the test. And for
loadaddr we have 11 unused bits, so we can have a conditionnal loadaddr too.
I think that taking vacancy are not so good, I have crazy idea when I came back
;-)

Now back to what you say, I was thinking that we make the test at start 
(before sending the job to the LSU), but if I correctly understand, we send
all and make the test at the same time, right ? That's strange.
 
> The only positive effect ist that CL/S will avoid some jumps. That is,
> in the rare case that you have code like
>
> 	if (condition) {
> 		*pointer = expression;
> 	}
> 
> with no preset and no else clause (or a volatile memory location),
> and with a trivial expression (something that is already present in a
> register, or can be computed with few additional instructions).  If
> the computation of the expression becomes more complex, a jump is the
> better choice. As soon as other statements precede or follow the assignment
> (inside the if clause), it is a must anyway.

If think that a jump could be a good solution actually because we only issue
one instruction per cycle, but what append if we issue more instructions ?
I mean that of course we make reflexion for our ISA with big register, but
we have the same reflexion with number of instructions per cycle.

> BTW: Good programmers avoid code like this anyway. Remember that the
> contents of `*pointer' remain undefined if `condition' evaluates to
> `false'. It's much better to write:
 
> 	if (condition) {
> 		*pointer = expression;
> 	}
> 	else {
> 		*pointer = default_value;
> 	}
> 
> or:
> 
> 	*pointer = condition ? expression : default_value;
> 
> which can be transformed to a conditional move.

I agree, but you know "good programmer"... ;-)

Cedric
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