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Re: [f-cpu] Powersave-function



Kim Enkovaara wrote:

> But clock gating is not always trivial. Normal timing tools have usually
> small problems if the clocks are gated and static timing analysis is not
> so straightforward. Also as far as I know there are some tricks how to
> remove the gating and not cause glitches to the clocks. Also some
> blocks can need few clocks to stabilize and that must be tought out in the
> powerup logic etc.

But other than the master clock, what clocks can be gated?
You still have to design for the worst case..

> I think it is easier to first do the chip and then think about power
> saving. Unless the chip consumes too much power and the power drain must
> be reduced. But there are easier ways to do this in the beginning. For
> example I/O lines should not be toggled unnecessarily and same applies to
> internal signals. Quite often the designs have default values for the
> busses and they have unnecessary toggling from
> old_value->default_value->new_value.

Note there are other ways to save power but they don't work on
highly pipelined systems as the logic needs time to pre-charge.
Ben.
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