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Re: [f-cpu] Powersave-function



On Thu, Jun 14, 2001 at 01:48:35PM +0300, Kim Enkovaara wrote:
[...]
> Easiest way to do power saving is clock gating. In CMOS logic only
> transitions consume power so removing the clock reduces the power
> consumption. Leakage is another problem with low voltage processes if
> ultralow power consumption is needed. For leakage there are quite many
> tricks, for example more complex gates or better internal protocols etc.
> 
> But clock gating is not always trivial. Normal timing tools have usually
> small problems if the clocks are gated and static timing analysis is not
> so straightforward. Also as far as I know there are some tricks how to
> remove the gating and not cause glitches to the clocks. Also some
> blocks can need few clocks to stabilize and that must be tought out in the
> powerup logic etc.

What about a variable internal clock?  Using a (programmable) NCO,
we could increase/decrease the clock frequency without any glitches.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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