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[f-cpu] manual update



p195 Chapter 3
- We should thought away the reference to the xbar. If in our head xbar
== buses, it will not be the case of newcomers. 

- We can't impose that more than 2 register can't point on the same
cache line. What happen with :

foo (int toto, int tata)
{
  int a,b,c;
  int * pa, *pb, *pc;
  
  pa = &a;
  pb=&b;
  pc = &c;
}
a,b,c are allocate in the stack, so there are contigŁ in memory, so
there are on the same cache line.
We can't leave such enormous limitation to the fcpu.

- Memory stream are to differentiate data flow by not checking coherency
between them and then we could buffer write and note checking the adress
of an immediat following load. We absolutely never mind about the memory
technonoly used behind the memory controler (SDRAM bank in the manual
case). L2 cache are there to help the management. 

So we should change all of this in the manual. Comment ?

nicO

 
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