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Re: [f-cpu] use of 1r1w regfile for our 3r2w regfile



Le Vendredi 13 Juin 2003 18:02, Michael Riepe a écrit :
> On Fri, Jun 13, 2003 at 05:11:54PM +0200, nico@seul.org wrote:
> > To speed up regfile look up, we could use 4 1r1w regfile which introduice
> > 4r4w port . In case of colliding, one clock cycle is lost.
>
> Or two, in case of a 2r2w or 3r1w instruction.  With <m> operands and <n>
> results, there may be <m>+<n>-2 collisions -- no matter how many separate
> banks there are.  It's just less likely that a collision occurs with four
> banks instead of two or three, but I doubt that it's worth the effort.
>
> For target technologies that work on the transistor level, we should
> design our own multi-ported SRAM if nothing appropriate is available.
>
> In any other case, we'll have to use what's available.  Worst case is
> that we have to resort to ordinary latches with some stuff around them
> (2:1 muxes at the input, 64:1 muxes at the outputs).
>
> On the other hand, the meaning of "worst case" clearly depends on ones
> point of view.  You can't build a 5-port (3r2w) RAM from 2-port (1r1w)
> RAMs unless you put each register into its own bank (and then you
> could also have used latches which are probably smaller and faster).
> Therefore, you would have to adapt not only the scheduler but also
> the compiler to the kind of register set used (in particular, to the
> number of banks and the `interleaving factor', that is, the placement
> of individual registers).  This is what I consider the "worst case".

But is that good or not ? 4x 1r1w regifile will be ~30% faster than a true 
3r2w.

nicO
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