Re: [f-cpu] use of 1r1w regfile for our 3r2w regfile

[<nico@seul.org>]

> hello,
>
> Anup Gangwar wrote:
>
>>Hi,
>>
>>	I have been reading posts on this list for long but have never
>>posted any message myself. In my opinion going for simpler (less R+W
>> ports) RF's will be advantageous from two viewpoints:
>>
>>1. If we stick to at most 2R+2W ports then the CPU could easily work
>> with  FPGA technology a big+ while prototyping.
>>
>>
>
> this creates a problem : F-CPU is not meant to use *only* FPGA.
> so if we develop with FPGA in mind (call this a "least common feature
> problem")
> the design will not exploit all the potential of ASICs.
>
> and after all : even if a 3R2W RF is 3x slower than 1R1W, you're still
> overlooking something :
> it will *work* ! (look at Don's post).
>

*work* : it's not sure, more than 1r1w for internal SRAM is rare.

Bank:
+ faster clock
- common
- collision

multiported logic :
+ no collision
- slower clock
- should be done at transistor level (fast) or see of gate (mega slow)

I will try to synthesys the code of michael.

>>2. The larger the RF the slower it will be.
>>
> The RF has 63 registers that are *at least* 64-bit wide.
> so it's already slow from the start, right ?
>

Adding port slowdown things and 6 stage mul became a no-sens (when 3 or 2
will be enought).

nicO

<...>
> YG



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