[f-cpu] Simulating with GHDL

[Michael Riepe <michael@stud.uni-hannover.de>]

Hi guys,

I'm currently testing ghdl 0.6.  It's able to analyze my working sources,
and the simulation programs also run, with minor additions that I'll
include in my next release:  When a component is instantiated, there is
no default binding unless the entity name is "directly visible"; that is,
you need to add a use clause or configuration specification for it,
like this:

	component blah
		...
	end component;

	-- solution #1: use clause
	use work.blah;	-- or maybe work.all

	-- solution #2: configuration specification
	for all : blah use entity work.blah;

The first solution is more convenient because the configuration
specification has to be repeated in every nested block that instantiates
the component, while the use clause has to be specified only once.

If the entity is not directly visible and not bound by a configuration
specification (or an external configuration declaration), the component
will be unbound (that is, its "socket" will stay open) and the entity
testbenches will produce garbage.  Note: This is not a bug, the behavior
is specified in the VHDL Language Reference Manual.  At least that's
what I understood...

If you want to give ghdl a try, I suggest you use the following
commands:

	# analyze source file(s)
	ghdl -a --std=93 --ieee=synopsys file.vhdl ...

	# elaborate
	ghdl -e --std=93 --ieee=synopsys entity_name

	# simulate
	./entity_name

There's only one restriction: You need a recent glibc based
Linux/x86 system to run the ghdl binaries (available from
http://ghdl.free.fr/ghdl-0.6-i686-pc-linux.tar).

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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