[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: Rep:Re: [f-cpu] virtually or physically-addressed cache ?

From: "Yann Guidon" <whygee@f-cpu.org>

> changing the protection when switching the processes/tasks/threads
> looks ugly for me.

It is, if you use a process ID it only needs to happen for the shared memory

> > Alternatively/additionally you could use a segment based approach with
> > segment protection flags and just change the segment registers when
> > switching threads ... with variable sized segments that would work out
> > pretty well IMO, an important aspect is that it can work with SMT.
> i think that F-CPU is already complex enough with only paged/virtual
> adding segments woud be a mess. Unless you mean a "fence" mechanism,
> but then only a fence or a few shoud be active at a time.

With segments Im thinking of a set of registers which are indexed by the
MSB's of the address, the content of which replaces the "top" part of the
address. Each segment would have its own set of protection flags.

> Don't you think that a CPU with a decent number of TLB entries and a
> tagged cache is enough to make an OS that is not too hairy ?

Of course.


To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/