Re: Rep:Re: [f-cpu] virtually or physically-addressed cache ?

[Yann Guidon <whygee@f-cpu.org>]

hello !

i thought i'd sleep but...

Marco Al wrote:
> From: "Yann Guidon" <whygee@f-cpu.org>
> > changing the protection when switching the processes/tasks/threads
> > looks ugly for me.
> It is, if you use a process ID it only needs to happen for the shared memory
> though.

the problem with this kind of trrick is that there are always cases
when the simplifying trick doesn't apply, so only remain the drawbacks :-(

> > > Alternatively/additionally you could use a segment based approach with per
> > > segment protection flags and just change the segment registers when
> > > switching threads ... with variable sized segments that would work out
> > > pretty well IMO, an important aspect is that it can work with SMT.
> >
> > i think that F-CPU is already complex enough with only paged/virtual memory,
> > adding segments woud be a mess. Unless you mean a "fence" mechanism,
> > but then only a fence or a few shoud be active at a time.
> 
> With segments Im thinking of a set of registers which are indexed by the
> MSB's of the address, the content of which replaces the "top" part of the
> address. Each segment would have its own set of protection flags.

Don't pages do already do that ? ... huh ?

> > Don't you think that a CPU with a decent number of TLB entries and a physical
> > tagged cache is enough to make an OS that is not too hairy ?
> Of course.

i wish i could find THE trick that would solve all our problems...
life's fun when you find solutions.

> Marco


PS: i just found a page about the "CRAY/TERA MTA" computer :
http://www.sdsc.edu/~allans/wave.html
http://www.sdsc.edu/~allans/papers.html

WHYGEE
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