Re: [f-cpu] another DATE report

[nico <nicolas@seul.org>]

Sorry, i couldn't be at first jeudi. 

For the story about VCI, i have  contacted tghe guy from wishbone. He is
very please that we introduice new type of cycle in there buses. Maybe
such cycle could come from VCI ideas.

Wisbone is very (to much ?) simple. i propose to introduice 3 things :
- a cycle take only one cycle, so it's means that the signal must make
the following travel : master-arbiter-master-slave-master ! There is an
extention to introduce waiting cycle but you loose bandwith.
I propose to introduice interleave multi-cycle access. It look like the
new low latency DRAM from Infineon with a synchronous SRAM interface.
So, you send the adress to receive the grant from the arbitrer but then
you have n cycle bevore receiving or sending the data. But you could
rebegin an other transaction in between.

- a CAS 2 cycle. 2 consécutives load followed by 2 writes but atomic !
If there is problems, writes could not occur. 
 
- maybe things to manage cache L2 (from my point of view L2 is tied to
the DRAM controller, the L1 is tied to the CPU). None caching access for
example to avoid cache trashing.

nicO
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