Re: [f-cpu] second order prefetch in FC0

[Yann Guidon <whygee@f-cpu.org>]

hi,

Martin Devera wrote:

> > it's surprising but not improbable.
> > patents are now complex strategies and they have probably
> > made a string of patents to cover all parts and aspects,
> > rather than 1 patent describing the whole stuff,
> > just to be sure that there is no possibility to bypass the patent.
> >    
> > > Also in 21264 hw
> > > manual is no such data in cacheline ??
> > >      
> > or maybe it was 21364.
> >
> > If it is possible to do, it will probably be implemented in FC0
> > but i don't want to take risks.
> >    
> I understand. Maybe we could ask at comp.cpu.architecture as
> many people are there ...
i can access to comp.arch but comp.cpu.architecture is unknown in my 
server :-/

> I found some citations about multi-prefetch techniques so that
> maybe it is/was unpatentable prior art.
what is multiprefetch ?
is it several interleaved prefetches ?

> What would be holder of patent, DEC ? And in range 1990-1992
> I think.
>  
the technique i've described is more in the 1995/1998 range.
and it's really an excellent idea, but probably too complex to do first.
a decently working cache is necessary in the beginning,
then we can enhance it ....

> devik
>  
YG

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