Re: SR [was:Re: [f-cpu] delayed issue]

["Christophe Avoinne" <christophe.avoinne@laposte.net>]

----- Original Message -----
From: "nico" <nicolas.boulay@ifrance.com>
To: <f-cpu@seul.org>
Sent: Thursday, March 06, 2003 12:50 AM
Subject: SR [was:Re: [f-cpu] delayed issue]


> > >There is no need for a specific buses, only the use of direct
> > >addressing had an interrest.
> > >
> > >
> > ???
>
> Use set/get is like a load/store using direct adressing.
>
> >
> > >>3) what mess ?
> > >>
> > >The kind of linked-list that can't take nest interrupt that you speak
> > >about regularly. (shadow register could be far more easy...)
> > >
> > >
> > ???
> >
>
> SR was just for some constant reading, then you use it for system
> control(like for trap handling). Each time some dust are on the design
> pchout it send to SR, like a wide carpet.
>
> SR are slow because serialiased. SR can't be preserve by context switch
> because it sill be a mess. So only read is premit.
>
> We could also put register trap pointer,  TLB ... But register mapped
> seems so easier (don't forget that SR are direct mapped).
>


Just a precision, the ARM has a coprocessor interface : it can handle with
16 (or 15) coprocessors and has an small uniform set of instruction to help
to communicate between itself and a coprocessor. For example, the MMU
handling is done with the coprocessor number 15. It is a very good idea
because you can transfer ARM registers and CP15 registers to and fro, make
CP15 load or store address, etc. Whygee, if interested, just have a look on
S3C2410, ARM9 isa part and MMU part, where they explain how to handle MMU
coprocessor. That kind of interface could be very interesting for F-CPU to
add external coprocessor and have a more tighly coupled functions.

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