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Re: [f-cpu] New VHDL Stuff - Xilinx synteheis report
- To: Michael Riepe <michael@stud.uni-hannover.de>
- Subject: Re: [f-cpu] New VHDL Stuff - Xilinx synteheis report
- From: devik <devik@cdi.cz>
- Date: Mon, 31 Mar 2003 21:55:56 +0200 (CEST)
- Cc: <f-cpu@seul.org>
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- Delivered-to: f-cpu@seul.org
- Delivery-date: Mon, 31 Mar 2003 15:37:05 -0500
- In-reply-to: <20030331142755.27059@thrai.stud.uni-hannover.de>
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- Sender: owner-f-cpu@seul.org
So that, synthesis of old adder yelds 452 slices and runs
at 68 MHz. Thus new adder is both more complex and slightly
faster.
devik
On Mon, 31 Mar 2003, Michael Riepe wrote:
> Hi!
>
> > > Yep. Could you try the previous version of EU_ASU as well? I'd like
> > > to see if there is a timing difference.
> >
> > and could you send me the source ? I'm not sure what is
> > "the previous version" for sure. I need only
> > iasu.vhdl ..
>
> Attached. Note that this version also needs common/generic_adder.vhdl
> (but you already have that).
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