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Re: [f-cpu] New VHDL Stuff - Xilinx synteheis report

To: f-cpu@seul.org
Subject: Re: [f-cpu] New VHDL Stuff - Xilinx synteheis report
From: Michael Riepe <michael@stud.uni-hannover.de>
Date: Tue, 1 Apr 2003 01:19:18 +0200
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In-reply-to: <Pine.LNX.4.33.0303312154250.522-100000@devix>; from devik on Mon, Mar 31, 2003 at 09:55:56PM +0200
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On Mon, Mar 31, 2003 at 09:55:56PM +0200, devik wrote:
> So that, synthesis of old adder yelds 452 slices and runs
> at 68 MHz. Thus new adder is both more complex and slightly
> faster.

Good :)  I expected the former (there are several new functions) but I
wasn't sure about the latter.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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References:
- Re: [f-cpu] New VHDL Stuff - Xilinx synteheis report
  - From: devik <devik@cdi.cz>

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