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Re: [f-cpu] about Gaetan's work

'soir,

gaetan@xeberon.net wrote:


Yann Guidon a écrit :


Hello !

Gaetan will submit his report on friday, in a public session i believe.

Some of his working documents are at http://xeberon.net/temp/

and it's in french (translation will be done next)

those who have had the idea to read it probably remarked it :-)


and i'm proofreading some of it.
currently i'm looking at fcpu-fpu-adder-appendix.pdf

One remark :
generic (
  WIDTH : natural := 64
);

and an assertion that checks WIDTH mod 64 ....

F-CPU's data widths are powers of two, not all multiples of 64.
in fact i checked before with power of 2, but i saw Micheel doing this, i thought i
should also do this

--pragma synthesis_off
begin
assert (WIDTH >= 64) and (WIDTH mod 64 = 0)
report "width of IAdd must be an integer multiple of 64"
severity failure;
--pragma synthesis_on

Gaetan doesn't seem to use a cloning wrapper for handling
larger widths transparently. Did i miss a discussion ?
(highly probable)

it's more probable that Gaetan didn't make it in a good way...

"good" is not the right word.

here, you see, i don't go into big details,
however that's a structural thing for which i can help.
look at other units, such as the EU_ASU :
there is one implementation of a 64-bit adder,
and a wrapper that duplicates the unit.
You don't have to include pragmas in the "heart"
of the code with this method, you could
copy-paste MR's wrapper and change the interface.

furthermore, though it's not impossible to do it,
it makes few sense in general to have datapaths
that are not a power of two of bits.

For the rest, i still haven't read enough of your code and report.
if you need to correct a lot of your spelling, grammar
and conjugation problems, i can help however :-)
first hint : "décalage" has only one "l" :-)

@+
YG

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