[f-cpu] Shifter

[Michael Riepe <michael@stud.uni-hannover.de>]

Hi!

Here's another version of the shifter.  It now uses a 6-stage omega
network (in fact, a *reversed* omega network) for bitwise operations.
Additional changes:

	- cleaner, more regular code
	- since the core is basically a rotate unit, shifts are now
	  performed by `rotate-and-mask'. A second output holds the bits
	  that were lost, giving us `double' shifts for free (but only
	  the 2r2w ones; 3r1w double shifts are not supported).
	- as a consequence of the implementation, `bitrev' now has a
	  SIMD counterpart, `sbitrev'. `bitrevo' isn't supported.
	- performs both mixl and mixh (or expandl and expandh) at
	  the same time (2r2w).
	- can perform either byterev or sdup on two independent
	  input operands (2r2w).

I didn't test all extensions; I'd like to see synthesis reports before
I go on (maybe this is even slower than the last one).

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"

fcpu-shl-mr-20011102.tar.gz