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Re: [f-cpu] Shifter, like during the good old days ;p



------
elaborate Shuffle64 -gate_clock
Error: Can't determine type of aggregate or concat 
        in routine rotate line 181 in file
'/home/profelec/nboulay/perso/fcpu/shl/fcpu-shl-mr-20
011102/eu_shl/shuffle64.vhdl'
        called from Shuffle64 line 312 in file
'/home/profelec/nboulay/perso/fcpu/shl/fcpu-shl-m
r-20011102/eu_shl/shuffle64.vhdl' (HDL-123)
No designs were read
0
--------

nicO

Michael Riepe a écrit :
> 
> Hi!
> 
> Here's another version of the shifter.  It now uses a 6-stage omega
> network (in fact, a *reversed* omega network) for bitwise operations.
> Additional changes:
> 
>         - cleaner, more regular code
>         - since the core is basically a rotate unit, shifts are now
>           performed by `rotate-and-mask'. A second output holds the bits
>           that were lost, giving us `double' shifts for free (but only
>           the 2r2w ones; 3r1w double shifts are not supported).
>         - as a consequence of the implementation, `bitrev' now has a
>           SIMD counterpart, `sbitrev'. `bitrevo' isn't supported.
>         - performs both mixl and mixh (or expandl and expandh) at
>           the same time (2r2w).
>         - can perform either byterev or sdup on two independent
>           input operands (2r2w).
> 
> I didn't test all extensions; I'd like to see synthesis reports before
> I go on (maybe this is even slower than the last one).
> 
> --
>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
>  "All I wanna do is have a little fun before I die"
> 
>   ------------------------------------------------------------------------
>                                   Name: fcpu-shl-mr-20011102.tar.gz
>    fcpu-shl-mr-20011102.tar.gz    Type: Unix Tape Archive (application/x-tar)
>                               Encoding: base64
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