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[f-cpu] Turing Award rocks !


as if i had only that to do, i just browsed
through a pile of files i downloaded from the Net in september.
I clicked here and there, until i found a document named
cmicropipelines.pdf, a 19-pages paper written in 1989
by Ivan E. Sutherland (Turing Award) for the ACM
(Communications of the ACM, Volume 32, number 6, pages 720-738).
It describes a more or less interesting scheme for
a sort of asynchronous logic (what he refers to
"micropipelines"). Then at the bottom of page 727,
i found the picture that i put at http://f-cpu.seul.org/new/FF.gif.

I did not react to this the first time i saw this a few months ago.
However now it is clear : Connect the Capture and Pass signals
together (eventually inverting one signal, or swapping
the MUX inputs), and you have a wonderful 2-edges flip-flop !
It stores a new value during every clock edge and still outputs
the last values. This is perfect for a semi-custom F-CPU because
the pipeline stages are already so thin that FF and clocks cause
most of the problems. Clock skew is still not solved, but
it's not the goal : if we can latch one value per clock edge,
we don't need 2 edges for one "cycle", thus halving the power
consumption :-))) on top of that, it looks like a good surface/speed
compromise, compared to what i have seen with Alliance.

This kind of cell requires three 2-input inverting mux gates,
optionally with two additional inverters for the second version.
This is close to optimal. Stop me before i design the cell's layout
(and probably reinvent the wheel) ! :-P

Important note : whether we use this kind of cells or not is completely
independent from the F-CPU core. Whether a clock cycle contains one
or two edges does not change anything from the logic side or even
the scheduling. Sutherland describes a complete framework for
asynchonous logic that solves nicolas' and other's questions about
"contentions and bubbles in a long pipelined unit", i recommend nicO
to read this paper (i put it at seul.org). This is not
going to be used for FC0 but it is not yet possible to know what FC1
would look like.

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