Re: [f-cpu] whygee's Nth slaughtered ROP2 version

[nicO <nicolas.boulay@ifrance.com>]

Josh Fender a écrit :
> 
> Hi YG,
>   You may not remember me but I'm one of the lurkers who occationally runs
> your vhdl code through synthesis and place and route software.  The code
> you attached to your previous message runs through Synplify Pro with no
> errors or warnings.  Maybe a less useful, but more interesting, fact is
> that when placed in a Xilinx Virtex grade 6 chip it runs at 85MHz.  This
> number is calculated based on driving the input/output signals
> directly from/to pins on the FPGA, so on a real intergrated system the
> timing would probably be closer to 100MHz or possibly even better.
> 
>   On a slightly different note, I could test the unit in a real FPGA if
> you have any test vectors.
> 

It will be nice to note the multiplier unit too. Because technologie or
so much different : it's difficulte to make comparaison ! (on 0.18 µ,
the mul unit run almost at 500 Mhz, i don't remember exactly the number)

nicO

> - Josh
> 
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