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Re: [f-cpu] whygee's Nth slaughtered ROP2 version


Josh Fender wrote:
> Hi YG,
>   You may not remember me but I'm one of the lurkers who occationally runs
> your vhdl code through synthesis and place and route software.
i think you posted a few times already :-) welcome back !

> The code you attached to your previous message runs through Synplify Pro
> with no errors or warnings.
pfiew. the contrary would have been a bit surprising because it's
the most reworked unit i wrote :-)

>  Maybe a less useful, but more interesting, fact is
> that when placed in a Xilinx Virtex grade 6 chip it runs at 85MHz.
the little problem is that i don't know whether it's fas or slow.
recently, nicO announced that the shifter ran at 2.6ns on a different
technology, so it's difficult to compare. We can also
test different "architectures", particularly concerning the
"combine" strategy (whether my new method or Michael's is faster,
and on what target etc...)...

> This number is calculated based on driving the input/output signals
> directly from/to pins on the FPGA, so on a real intergrated system the
> timing would probably be closer to 100MHz or possibly even better.
that's a good news, right :-)

>   On a slightly different note, I could test the unit in a real FPGA if
> you have any test vectors.

i am about to do it, it should be ready within a few days.
however, i do test vectors for VHDL testbenches, not FPGA tests :
will you be able to adapt them ?

thank you again,

> - Josh
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