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Re: [f-cpu] I'm still in the warmup phase ;-)

I'm speaking German too - but let's stick to English to avoid excluding others.

should get a simple design running before adding fancy engines.

we've been there before :-)
I can imagine very well -- LOL

We already have such an engine, sort of:

# load parameters...
loadcons $0x7770632d30303066, r1 # that's "f000-cpu"
loadcons $0x7070707070707070, r2 # that's 8 times a 'p'
# and here we go:
xnor.and.b r1, r2, r3
# matching bytes are 0xff, others 0x00
notice the single-cycle operation :-P
Hmmm... Exnor will make equal bits 1 and unequal bits 0 that's well known.
So "and.b" is an FC0 specific feature ANDing all bits in their respective byte?
Looks great! So in order to check whether a needle is in a haystack
i'll just race throught the memory and compare the xnor.and.b to zero, 8 chars
a bunch. If nonzero, locate it precisely. If we use this in strncmp-like functions,
we'll run databases and such pretty fast. WOW!

I still have to get used again to that Intel-like opcode stuff and reverse-reading
the bytes in the code -- the good old Endian issues. You alredy agreed on an
opcode for the FC0?

however, the portability problem is very critical.

[...] The written VHDL code
will need many modifications before running on another board, let
alone another family of FPGA, and not even considering another brand.
Ooops! Sounds like we need an abstraction layer. And implies that if we get
it running on CPLDs, we can't use the same VHDL code for the ASIC -- Horrible!
I don't know VHDL yet. I thought it's a connect-this-to-that language that
is independent of the physical layout. Or was that something SPICE-like?

>Do we need more pseudo-registers for memory access?
>what do you mean here ?

That the CPU core looks at the memory through a "window" that looks like
two registers. This can significantly reduce opcode space.

Example: r60 and r61 are the memory access window. Load the address into r60.
If we read from r61, we read the memory at the address given in r60. Write works
in a similar way.

Instead of
r01 := [0x00000ha150373135]
we issue
r60 := 0x00000ha150373135
r01 := r61

Disadvantage: more difficult to see "vom Schiff aus" which MOVE commands use
many clock cycles.
We will need at least 2 (better 3 or 4) windows of that kind, sacrifying up to 8 registers.

* The majority of computer users needs rather data movers than computers (i.e. machines performing calculations).
>but did you hear about the "memory bandwidth barreer" ?
>F-CPU is designed to be good at computing, it's a fact.
Yep. Maybe we later add an unit outside the FC0 doing
memory block moves, avoiding occupying the CPU's
memory bus. I think the AMIGA had such an engine.

>btw, welcome aboard :-)
Thanks, captain.

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