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Re: [f-cpu] Re: La MMU du f-cpu


Pierre Tardy wrote:

The next steps may be to implement the Fetcher then the LSU then the caches.. At this time, I 've no idea  how long it can take us.


I have written about the LSU because we spoke about a simulation that would
be more or less acurate from the memory bus point of view. Because
the LSU & fetcher cache stuffs, this has an important impact.

Now, if you don't care about modeling the bus transactions, don't worry.


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