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Re: [f-cpu] Smooth Register backup issues...


Michael Riepe wrote:

Hi #4,

Christophe Avoinne wrote:

What I seem to understand is that you want to use a CMB switching far all
interrupts or exceptions, which sounds like a task gate. Is it really a good
idea ?
Heck no. That's exactly what I do NOT want. Interrupts must be fast. But there is a big difference between Intel CPUs and the F-CPU: We don't have stack push/pop instructions, and we don't have `direct load/store' instructions either. We need to clobber at least one register in order to save the rest (for the pointer).
That's why, in the absence of SRB, a trap handler can use "scratch" SRs.
See my other post about that.

With SRB, all registers used inside the ISR are saved automatically, and restored when the ISR exits. Note that it may not be necessary to save/restore ALL of them
SRB can't be interrupted to start another SRB but
it can be interrupted when the previous "task" is restored.
So yes, SRB is also adapted to short interrupts,
the flags keep track of what register has been used
by the handling routine so it can restore the right
registers only.

-- if the SRB is smart enough (should be labelled "smart register backup" ;-).

Nested interrupts remain a problem, however.
no, there are well known solutions.

Use your good sense, Luke :-)


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