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Re: [f-cpu] 'make it work' or 'make it fast' ?

Yann Guidon wrote:
> hi,
> since i am studying at ASIME, i have learnt some
> basics about using the "homemade" Alliance toolchain.
> I can make several reproaches about it : it is "a bit heavy",
> does not comply to the VHDL standard coding practices,
> but i begin to realize that it is not really a VHDL tool :
> in fact it is more a synthesis tool. It has the advantage
> that you can design masks relatively easily and quickly.

Has it been upgraded lately - the libraries may be outdated?
I only problem with the tools I can think of is
the fact that the timing calculation program is not free. Sure
we can route the
chip but we can't tell you what the delays are. :(
> However, from what i can see, the use of their precharacterised
> library is not the best way to make a "fast" CPU, if you consider
> that if you want to make custom ASIC, you want to get all
> the power you expect from this. On one side, you reduce the
> pressure on the post-synthesis tools (timing/parasitics/etc)
> but on the other side, you can get almost the same speed
> (and probably more) with the latest FPGAs (who support the
> most recent synthesis algorithms with fully VHDL compliant sources).
> This is because, from what i have seen, their strategy is
> underefficient, particularly with P&R and post-layout compression
> (there's often wasted surface). This is maybe my PCB designer's eyes
> that tell me that.

The only real way is design the cpu by hand to get the best use
of space. Alliance
looks to one of the better ( not that I have used many tools )
for routing.
With the modern chips routing I guess is half the space used in
a die.
> But i can't deny that having a working F-CPU sooner is attracting.
> So there's the old dilemma : do we sacrifice source portability,
> clock speed and high-level synthesis ? Or do we accept to go the
> route of early prototypes ?
> It would be cool if Alliance accepted VHDL'93 sources, or even
> FOR .. GENERATE loops !!!

Nothing is portable -- schematics are often too low level. HDL's
are too abstract to map well to hardware.FPGA's all have
different logic cell functionality. I would personally go with
if there was a portable way of creating them. 
From what little I have been playing with FPGA's is that they
tend to routing bound rather than gate bound. About 25%-33% of a
fpga needs to be free so you can route and place your design.
If we get a FPGA working then hopefully one can use a FPGA to
ASIC program to get prototypes, until one has the resources to
do the whole ASIC BY HAND.

Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.
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