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Re: [f-cpu] 'make it work' or 'make it fast' ?


nicO wrote:
> Yann Guidon a écrit :
> > hi,
> >
> > since i am studying at ASIME, i have learnt some
> > basics about using the "homemade" Alliance toolchain.
> > But i can't deny that having a working F-CPU sooner is attracting.
> > So there's the old dilemma : do we sacrifice source portability,
> > clock speed and high-level synthesis ? Or do we accept to go the
> > route of early prototypes ?
> You need to use the library from a foundry. Does Alliance accept
> synopsys library file ?

i don't know. It seems that Alliance has its own "standard library"
which can be "mapped" to another one if needed (you'll have to go
through the renaming of a few hundreds of files and their port declaration).

> Could you create SDF file to simulate it with timing (after synthesys)?
i don't know. i'm here since one week only, but i have seen that it
is possible to run post-synthesis simulations (gate delays, no wire delay)
using their precharacterized cells. i'll know more about it within
a few months.

> > It would be cool if Alliance accepted VHDL'93 sources, or even
> > FOR .. GENERATE loops !!!
> Alliance doesn't support "process", too...

that, too.
And they declare FlipFlops with ... guarded blok :-(

> On of your teacher M Jacome made a thesis to write a wrapper from
> "clean" synposys VHDL to dirty alliance VHDL.
we will probably have to use such a "wrapper" technique one day.
Alliance is modular and designed in this perspective.

However, i still think that Alliance-generated masks are underefficient.
One example : their cells are abutted linearly but doesn't take into
account the upper and lower rows. One trick is to flip the cells
of every odd rows, so you can merge the Vdd rail with the row below,
and the Vss rail with the above row. You can also merge the wells
to make a wider one.

Oh btw, during nov/dec, i'll have to make a MIPS CPU (pseudo-R3000).
i'm ashamed to say that it is the microprogrammed one ...

> nicO
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