Re: [f-cpu] 2R2W SHL

[Michael Riepe <michael@stud.uni-hannover.de>]

On Mon, Oct 08, 2001 at 11:08:52AM +0200, whygee@club-internet.fr wrote:
> hello,
> 
> IIRC michael is designing the SHL unit. I have a little
> suggestion : what about an instruction that does a 2R2W shift ?
> that is : one register gets the "normal" output of the shift,
> and the 2nd register gets the "shifted out" bits.
> the ROR/ROL instructions would be a OR of the two results.

That's the way I do rotates now -- I stuff the input vector with zeroes,
do a double-size shift, and OR the upper and lower half (it's a little
more complex when SIMD is involved, but that's it, basically).

The alternative approach is to use rotates as the basic element, and
mask the unused bits when you're doing a shift operation.  In this case,
you can get the `double width shift' result with two separate masks.

BTW: did somebody synthesize the alternative SHL core (the Rotate64
entity) I postet on Sep 28?  I'm still interested in some numbers...

> This is useful when a lot of bitblt is done, for graphics and
> bit string insertion/extraction... And there is no need to
> specify the shift direction because it is swapped when the destination
> registers are swapped :-)

But the interpretation of the shift count is also changed ;)

> any comment ?

Yep... I like the idea.  How do we call it, dshiftl? shiftd? shiftx?

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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