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Re: [f-cpu] X-Bar replacement and PoC of massiv-parallel-computing, hints?

On Mon, Oct 08, 2001 at 09:43:05PM +0200, Andreas Romeyke wrote:
> Hash: SHA1
> Hello,
> In a lecture about uController I had the idea of following architecture:
> Controller <-> RAM
>     |
>  +--+--+-----+-----+ ...
>  |     |     |     |
> ALU1  ALU2  ALU3  ALU4 
> Every ALU is very simple, it has 2 connections to a fast 2-wired serial 
> bus and 8 lines to hardwire the ALU-adress. Every ALU has a serial bus
> de/encoder, a queue/register-set of 16 entries with static length and
> contains basic functions like "add", "shift"/"ror"/"ashift", "xor", "and",
> "or", "not" on 8-bit basis.

I'd rather use an array of ALUs, with separate row and column buses
and dedicated links to their neighbours (much like the cells in an
FPGA).  Or maybe a ring.

The second point is: why do you want to use S/P and P/S converters?
Those operations can be done bitwise, (including ADD/SUB if you send
the least significant bit first and save the carry bit at each cycle).

> Can we use the concept of 2-wired bus with serial de/encoder on every unit
> in f-cpu instead x-bar? 

That's too slow.  Remember that the bus must be much faster than the
EUs, since we'll only be able to issue one instruction every 64 bus
clock ticks (if there are seperate buses for each operand).

 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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