Re: [f-cpu] freeze signal

[Yann Guidon <whygee@f-cpu.org>]

hello,

nicO wrote:
> whygee@club-internet.fr a écrit :
> > hi,
> > >De: <nicolas.boulay@ifrance.com>
> >
> > >Is it possible to add a signal to the entities to
> > >completly freeze its output. It's different from
> > >enable. The freeze signal must stop the pipeline or
> > >at least the output port of the unit, no new data
> > >should get out in the result port.
> > >
> > >We absolutely need this kind of stuff to handel unit
> > >with a latency more than 1 (to manage the fact to
> > >have 2 data could be ready in the same time)
> > >
> > >Any comment ?
> >
> > it's useless : writeback hazards are detected at decode/issue stage.
> > No instruction is issued (that is : freeze at decode) when we detect that
> > we won't be able to writeback in the future.
> >
> > hope this refreshes some memory :-)
> 
> Maybe in your theoretical scheduler but i wait to see it in real code.
> Make a system which predict the future, why not ? But it will take (i
> think) a lot of area (some calculation to do ?). At least, i wait the
> algorythme.

i guess that you understand that it is not the best time to write the
code now. Of course the system can predict the future : the scheduling
of every instruction is specified in the manual and conditioned by the
behaviour and structure of every execution unit. I and it knows that
if a ADD instruction is emitted, the result will be available on the "Xbar"
3 cycles later for another instruction. If you find another instruction
without dependency after the ADD, you know that you must not issue it if
the EU latency is 1, because the result would conflit with the ADD result
on the Xbar unless the results are both a single value (because there are
2 write buses). The latency of the instructions can be written into
a lookup table (which is generated when compiling the EUs).

As for the algorithm :
 * decode/R7 read stage : read/get all the flags, lookup the opcode and
   flags into the LUT, check if the registers are ready and if there are
   available write slots on the Xbar.
 * Xbar/issue stage : decide if we issue the instruction (big AND/OR),
   insert the instruction in the write slot.

You see that you can construct this only when all other elements are
available : Xbar mechanisms, some EUs, Registers, flags, ...

I have no time nor free brain cells for this now. I am already trying
to find a solution for the synthesis problem, and configuring my computers.

sorry for not being allmighty,
> nicO
WHYGEE
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