Re: [f-cpu] ROP2 unit

[Yann Guidon <whygee@f-cpu.org>]

hi,

nicO wrote:
> Yann Guidon a écrit :
> <..>
> > -- YG> warning : huge fanous ! 1->64 for 4 signals, i hope that the synthesiser
> > -- will generate the proper buffer tree.
> 
> You never _never_  take care of such low level stuff. You will take care
> of it during problem at the synthesys stage. Keep the code simple and
> understandable. In such udge project it's the most important thing.

ok i anticipate, but i want to see where the problems will arise.
propagating 1 bit to 64 or more wires can be a limiting factor for
the operating frequency, and i am more sensitive to this problem now.

However, speaking about simplicity, can you find a trick to remove the
't' signal ? simili and vanilla refuse to put an agregate as argument of
a with..select. I also would like to get rid of the for-generate loop
but it's likely to be impossible to make a vector version, since the
MUX selectors are vectors themselves...

> nicO
WHYGEE
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