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Re: Re: [f-cpu] X-Bar replacement and PoC of massiv-parallel-computing, hints?
on top of all that, ternary coding is not suitable for CMOS.
read some electrical/electronical books about this subject
(i have some courses about it currently) : it is not possible
to have a third stable electrical level in complementary
Michael Riepe <email@example.com> :
>On Tue, Oct 09, 2001 at 10:29:54PM +0200, Andreas Romeyke wrote:
>> > The second point is: why do you want to use S/P and P/S converters?
>> Why not?
that is secondary, compared to the rest ;-)
>> S/P and vice versa is easy to build. Today, I have some discussions, a
>> 2-wired bus with +high, low and -high levels are very fast, because we
>> have signals like this:
>> a: +high low -high +high -high low
>> b: -high low +high -high +high low
>> so the sum of levels on a and b are always zero.
so what ?
>> Also with 3 logic levels
>> we have the the chance to reduce/compress bitrate with 4b3t-code like in
>> ISDN-systems (remember: 4 clocks in binary code means 16 combinations, 3
>> clocks in ternary code means 27 combinations, there also some ternärcodes
>> free to use as sync)
>You'll have to decode two `tits' (Ternary digITS ;) into 3 bits, then.
>Everything else is too complex.
on top of that, "digital" CMOS is not suited to "analog" functions
(the tolerances and the library cells are not available).
>> > > Can we use the concept of 2-wired bus with serial de/encoder on every unit
>> > > in f-cpu instead x-bar?
>> > That's too slow. Remember that the bus must be much faster than the
>> > EUs, since we'll only be able to issue one instruction every 64 bus
>> > clock ticks (if there are seperate buses for each operand).
>> No, it is not, if we have a EUs-clock of 1ms, we have on serial bus a
>> clock of:
>> - ---------------- * 3 => bits/1ms + overhead_of_headers
>> 4 * (sum of EUs)
>That's 6 times the EU clock if there are 8 EUs... and if an EU runs at
>1 GHz, your serial bus will run at 6 GHz?!
we can't do that. F-CPU is meant to work at the maximum clock speed
already. The logic behind that is : if one part of the device runs faster
than the rest, why can't the others run faster ? Furthermore, having
everything fully synchronous and with one clock only is so much easier
to debug and understand.
>> But, one serial bus with 2 lines in above described technology is easier
>> in handling than a parallel bus with 64 or more lines with a line clock
>> less than serial.
>> Remember, a parallel bus is a capacity and frequency-sensitive and costs
>> many of logic (see X-bar or Shifting-unit).
>Buses are evil anyway, whether they have 2 lines or 200 ;)
like evils, they are unfortunately necessary ...
"il faut de tout pour faire un monde"...
> Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
> "All I wanna do is have a little fun before I die"
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