Re: [f-cpu] freeze signal

[Michael Riepe <michael@stud.uni-hannover.de>]

On Wed, Oct 10, 2001 at 12:07:42AM +0100, Yann Guidon wrote:
[...]
> when you "assemble" the EU slices together, you implement
> the "glue" with registers in the top level. For example, the
> ROP2 EU is made of 2 main files : one does the predecoding
> (+ fanout) and overlaps the Xbar read stage, and the other
> file "does" the ROP2/mux operation.
> 
> When you create a testbench, you can "stick" the units together
> with wires, to avoid the latency management. When you implement
> the pipeline, you simply put pipe registers in the middle.
> 
> However, some code designed by Michael is not like that,
> but allows the specification of what pipeline depth is desired.
[...]

I'm afraid that feature is gone forever.  It's easier to rewrite the
unit for a different pipeline depth than make it configurable.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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