Re: [f-cpu] freeze signal

[Michael Riepe <michael@stud.uni-hannover.de>]

On Tue, Oct 09, 2001 at 10:51:04PM -0400, nicO wrote:
> Michael Riepe a écrit :
[...]
> > Currently, the EUs contain no input or output registers at all; they're
> > supposed to be added at the next higher level.
> > 
> 
> So how do you make the pipeline, i miss some thing !

Inside the EUs, the registers are already there.  I can also add registers
to the in/out ports, if that is more convenient.  But it's IMHO better
to add them at the outer level, in case they need special control lines.

> > > We absolutely need this kind of stuff to handel unit
> > > with a latency more than 1 (to manage the fact to
> > > have 2 data could be ready in the same time)
> > 
> > The scheduler has to take care of that.  It must delay the instruction
> > if there is no free "transport slot".
> 
> Yep, you must insert a delay so you must at least stop the current flow
> or you could try to predict the cas e (but i wait an algorythme for
> that). In the first case, i need a signal to stop the pipeline (or stop
> to produice output) to insert an empty slot.

No, you just don't issue the instruction.  The pipeline will contain a
"bubble" -- meaningless data -- that is ignored.  Or, if it's one of
my EUs that has a clock enable input, the unused stages will be stopped
(while the active stages still finish other instructions).

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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