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Re: [f-cpu] registers
----- Original Message -----
From: "Nicolas Boulay" <nicolas.boulay@ifrance.com>
To: <f-cpu@seul.org>
Sent: Thursday, October 03, 2002 1:18 PM
Subject: [f-cpu] registers
[You]
That's not a bad point because there is very few case where you have to
use integer operation on flotting point number. So it's 2 class of
number with no real operation crossover. But this is also the case for
Fcpu : why mixing register bank for simple integer and vector ?
{I}
I think it is what you all would like to do : sharing the same register-bank
regardless with integer or float, single or vector modes.
[You]
Nowadays we too often think about 64 bits register length. so 64 == the
biggest int number. But in fact, the most interresting vector size is
256 bits.
As you can see, using a register of 256 for storing an integer of 64
bits is a big waste ! Look at our programmation api. We always have 3 or
4 pointers in the register set, so 3/4 of the register will never be
used 95% of the time, what a waist, don't you think ?
{I}
Okay, single integer can be only in 64-bit even if physically they are 256
bit. So you prefer to split and use a different register-bank instead. The
trouble if we consider using vector integer registers are much more
underused than single integer registers, well we still waste memory indeed
for 95% of the time wherever the 3/4 of 256-bit for registers are physically
located :).
P.S.: waist = taille,ceinture (fr), you mean "waste" ;)
[You]
I don't think we should split fp and int register but SIMD and scalar
number.
Why not having 2 registers bank, one SIMD, the other Scalar ? This add
1/4 of memory content inside the cpu but double the number of usable
registers.
{I}
So we would switch one of the two register-banks through the SIMD bit in the
instruction format ?
What do you mean by doubling the number of usable registers ? as far as I
know, we can only access 64 registers at most as a range, so if you want to
transfer between scalar integer registers and vector integer registers, it
would be impossible to do so since we cannot mix both through the SIMD bit
setting.
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