Re: [f-cpu] Re: Testing Hardware

[Michael Riepe <michael@stud.uni-hannover.de>]

On Thu, Sep 06, 2001 at 10:47:02AM +0300, Kim Enkovaara wrote:
[...]
> I compiled the multiplier to VirtexII 6000-6 chip with Synplify. Synplify
> only wanted ~350M mem maximum during the compilation. The compilation
> took time 2 hours.
> 
> The speed was ~23MHz and utilization 54%. I did not optimize the design
> for speed and I didn't use retiming or pipelining options.
> 
> During the compilation I got the following warnings:
> Synthesizing work.imul64.behave_1
> @W:"/home/kenkovaa/personal/fcpu-mr-20010905/eu_imu/imul64.vhdl":173:27:173:29|S
> ignal clk in the sensitivity list is not used in the process

That's because Imul64 is not pipelined by default.  Please try the EU_IMU
entity (in imu.vhdl).  It includes Imul64 in its pipelined (6-stage) form
which should run faster (and take longer to compile, of course ;).

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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