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Re: [f-cpu] Re: Testing Hardware

On Fri, Sep 07, 2001 at 10:29:38AM +0300, Kim Enkovaara wrote:
> OK, I resynthesized the multiplier. Actually the compilation went much
> faster (little over 1 hour only). Also this time I did the synthesis
> without any speed constraints. The results were following with the same
> VirtexII 6000-6 bf957.
> Speed: ~72MHz

Is that good or bad for that particular FPGA?

> Utilization: 29%

How can it become *smaller* when pipelining is turned on?
Or is that caused by the missing speed constraints?

> I can try the same with some speed constaints and with retiming. But that
> slows down the compilation quite much.

I know...

 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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