Re: [f-cpu] New way of doing testbench

[Kim Enkovaara <kenkovaa@cc.hut.fi>]

On Mon, 10 Sep 2001, nicO wrote:

> http://www.testbuilder.net/resources.thtml
> 
> Maybe a good way to write a testbench for vhdl. I don't if it could work
> with free HDL or Simili.

Usually the interfaces to simulators are the difficult part of new
Verification languages and class libraries. The biggest commercial
simulators are usually well supported. Altough all features are not
supported in all simulators. For example Vera supports Temporal
expressions only with VCS currently. With Verilog the interfaces are
usually easier because PLI is well standardized. There is not yet standard
FLI for VHDL.

> It's a way to interface HDL and C++. It look very nice and it's free !

I wrote my masters thesis about Object Oriented ASIC vericiation, so
methodology is quite familiar for me. I have written with Synopsys VERA
one big testbench (30kloc). And now I have much more complex TB under
construction. I would not go back to VHDL testbenches. OO methodology and
higher level languages just make coding so much easier. Espaecially when
the TB complexity is all the time rising.

<start commercial>
Synopsys VERA has one very nice feature for CPU testing but unfortunately
the tool is commercial. VERA stream generator can generate quite easily
random but sane instruction stream. The instruction set is just described
with BNF and after that the generator can generate instructions.
I have heard that stream generator was developed for Sun Sparc
verification originally.
</end commercial>

=============================================================================
Mr. Kim Enkovaara   | kim.enkovaara@iki.fi | Microelectronic Riemannian
Vasamatie 1 C 16    | IRC: embo            | curved-space fault in
02630 Espoo         |                      | write-only file system

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