Re: [f-cpu] License issues GPL/LGPL and Juergen Goeritz' SoC

[Yann Guidon <whygee@f-cpu.org>]

hi,

nicO wrote:
> Michael Riepe a écrit :
> <...>
> > > My current view for a "decent" F-CPU chip is :
> > > - SDRAM (DDR/whatever) direct interface with the core
> > > - onchip L1 cache (low latency)
> > > - onchip L2 with very wide words, such as suggested by nicO, ie with DRAM,
> > >   so we can do very wide SIMD computations
> >
> No, don't mix things. I think as leon. It's like a canonical cpu. Leon
> are core+L1 cache then it used AMBA bus to connect memory controleur and
> so on (UART...). You could what ever speed you by enlarge the bus.
> Wichbone coulb be extend 256 bits for internal use.
> 
> So fcpu core will only be the core+cache(unified or separate). All
> others things could be include in a "plateforme". I think about
> controler, L2 cache but we can add interrupt controler and so on (IO
> quick link ). Imagine a router, it don't need SDRAM.
> 
> So to the outside world, we could have coprocessor interface (as leon ?)
> + bus interface (wishbone). That's could clairly defined API.

we have no defined interface yet. I don't think it will be necessary before
maybe 6 months (optimistic) because we have to completely design the
"execution pipeline" before we can do the memory I/O. We have enough time
to discuss this, obviously :-)

> nicO
WHYGEE
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