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[Fwd: [firstname.lastname@example.org: Re: [f-cpu] binary streams]]
- To: fm <email@example.com>
- Subject: [Fwd: [firstname.lastname@example.org: Re: [f-cpu] binary streams]]
- From: Yann Guidon <email@example.com>
- Date: Sun, 16 Sep 2001 00:42:56 +0200
- Delivered-To: firstname.lastname@example.org
- Delivery-Date: Sat, 15 Sep 2001 18:43:36 -0400
- Organization: http://www.f-cpu.org
- Reply-To: email@example.com
- Sender: firstname.lastname@example.org
it seems that these mails did not go to the list.
sorry for the delay.
----- Forwarded message from Kim Enkovaara <email@example.com> -----
From: Kim Enkovaara <firstname.lastname@example.org>
Subject: Re: [f-cpu] binary streams
On Thu, 13 Sep 2001, Yann Guidon wrote:
> > > by the following code :
> > ...
> > > variable c : character;
> > I think this is the problem. Define this as bit_vector or
> > std_logic_vector. After that binary mode reading should work. Character is
> > defined differently.
> i am not sure to understand what you said.
> I have already tried (well, with simili) to output std-ulogic_vectors
> and it uses one byte per bit (each bytt represents the different possible
> states of the corresponding bit). i don't understand what you mean by
> "Character is defined differently." I have read two (rather exhaustive) VHDL
> books in the subject and they did not address that point.
For character definition check the VHDL language definition. Character is
type character is ( nul,soh,stx,etx.....);
In some simulators I remeber seeing bug reports about the behavior of
character when considered as just byte. I just tried with Modelsim 5.5d
and the character version works just fine also. On the other hand
the version I tought (type foo is range 0 to 255) was little odd. It read
whole integers and didn't even complain that the values were out of
range, but that might be OK, the files were identical. I don't have LRM in
my shelf. The bit_vector came from one of my old test benches and that
actually was reading bits directly, sorry.
And about VHDL books, the only good one I have found is "The Designers
Guide to VHDL, Peter J Ashenden" There is a new edition of the book also,
that just came. And the Students guide to VHDL by the same writer is also
good book, but quite limited. For synthesis the best material is from
Synopsys training courses and FPGA tool manuals.
Mr. Kim Enkovaara | email@example.com | Microelectronic Riemannian
Vasamatie 1 C 16 | IRC: embo | curved-space fault in
02630 Espoo | | write-only file system
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