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Re: [f-cpu] Something new to play with :)



On Mon, 24 Sep 2001, Yann Guidon wrote:

> > We should take some chip as a reference and always synthesize for it.
> > Otherwise the results are not comparable. But to even get some feeling I
> > synthesized this block to Virte2 (XCV2V1000-BG575-6) and got following
> > results:
> > 
> > Speed: 66MHz (optimized for speed, no special tricks)
> wow :-)
> what is the fastest thing you have synthesised for this device ?

That is quite difficult question to answer, but to give some ideas how
fast it is (all one stage):

64-bit adder + reset: 143MHz (optimized by the synthesizer)
64-bit multiplier + reset: 62MHz (uses internal 16x16 multiplier macros)

> > Utilization: 30%
> wow :-/
> How big is it btw ?

It's quite big, but it is easeir to check the architecture from the Xilinx
manuals that are freely downloadable in the net. It would take too much
space to explain the architecture.

> this is why i prefered to use 4-in muxes :-)
> 
> Can you track where the critical datapaths are located ?
> Can you try on the (new) ROP2 unit ?

I'll copy some bits of the long report. First the high loads and what was
replicated during the synthesis.


Net buffering Report for view:work.Shuffle64(behave_1):
B_c[0] - loads: 185, segments 2, buffering source
B_c[1] - loads: 240, segments 3, buffering source
B_c[2] - loads: 230, segments 3, buffering source
pin:O inst:hi_and3_0[6] of VIRTEX.LUT3(PRIM) - loads: 78, segments 2,
replicating source
pin:O inst:simd_shuffle.1.hi_sel_un1_hi of VIRTEX.LUT2(PRIM) - loads: 52,
segments 2, replicating source
pin:O inst:simd_shuffle.2.hi_sel_un1_hi_3 of VIRTEX.LUT2(PRIM) - loads:
113, segments 3, replicating source
Added 8 Buffers
Added 0 Registers via replication
Added 4 LUTs via replication


Here are few critical paths:



A Critical Path with worst case slack = -10.0 ns:  

The start and the end point of this path are clocked by the System
Instance/Net                                               Pin      Pin
Arrival     Delta     Fan
Name                                         Type          Name     Dir
Time        Delay     Out
-----------------------------------------------------------------------------------------------------
                                             Shuffle64     View                                      
B[63:0]                                      Port          B[0]     Out
0.0         0.0          
B[0]                                         Net
1  
B_ibuf[0]                                    IBUF          I        In
0.0                      
B_ibuf[0]                                    IBUF          O        Out
0.9         0.9          
B_c[0]                                       Net
2  
B_c_0[0]                                     BUF           I        In
0.9                      
B_c_0[0]                                     BUF           O        Out
3.1         2.2          
B_c_0[0]                                     Net
111
tt_1_0[8]                                    LUT3          I2       In
3.1                      
tt_1_0[8]                                    LUT3          O        Out
4.1         1.0          
N_1396                                       Net
3  
tt_6[4]                                      MUXF5         S        In
4.1                      
tt_6[4]                                      MUXF5         O        Out
5.4         1.4          
N_791                                        Net
3  
tt_7[8]                                      LUT3          I0       In
5.4                      
tt_7[8]                                      LUT3          O        Out
6.7         1.3          
tt[8]                                        Net
8  
simd_shuffle.1.hi_sel_yy_1_iv_0.G_2884_s     LUT4          I2       In
6.7                      
simd_shuffle.1.hi_sel_yy_1_iv_0.G_2884_s     LUT4          O        Out
7.5         0.8          
N_6301                                       Net
1  
simd_shuffle.1.hi_sel_yy_1_iv_0.G_2884       LUT3          I0       In
7.5                      
simd_shuffle.1.hi_sel_yy_1_iv_0.G_2884       LUT3          O        Out
8.3         0.8          
N_4580                                       Net
1  
simd_shuffle.1.hi_sel_yy_1_iv[0]             MUXF5         S        In
8.3                      
simd_shuffle.1.hi_sel_yy_1_iv[0]             MUXF5         O        Out
9.6         1.3          
simd_shuffle.1.hi_sel_yy_1[0]                Net
2  
Y_iv_8.G_3830                                LUT4          I2       In
9.6                      
Y_iv_8.G_3830                                LUT4          O        Out
10.3        0.8          
N_5526                                       Net
1  
Y_iv_8.G_3832                                LUT4          I0       In
10.3                     
Y_iv_8.G_3832                                LUT4          O        Out
11.1        0.8          
N_5528                                       Net
1  
Y_iv[8]                                      LUT4          I0       In
11.1                     
Y_iv[8]                                      LUT4          O        Out
11.6        0.4          
Y_c[8]                                       Net
1  
Y_obuf[8]                                    OBUF_F_24     I        In
11.6                     
Y_obuf[8]                                    OBUF_F_24     O        Out
15.0        3.5          
Y[8]                                         Net
1  
Y[63:0]                                      Port          Y[8]     In
15.0                     
=====================================================================================================
This path has no setup requirement

A Critical Path with worst case slack = -9.7 ns:  

The start and the end point of this path are clocked by the System
Instance/Net                                    Pin       Pin     Arrival
Delta     Fan
Name                              Type          Name      Dir     Time
Delay     Out
-------------------------------------------------------------------------------------------
                                  Shuffle64     View                                       
B[63:0]                           Port          B[1]      Out     0.0
0.0          
B[1]                              Net
1  
B_ibuf[1]                         IBUF          I         In      0.0                      
B_ibuf[1]                         IBUF          O         Out     0.9
0.9          
B_c[1]                            Net
3  
B_c_1[1]                          BUF           I         In      0.9                      
B_c_1[1]                          BUF           O         Out     3.1
2.2          
B_c_1[1]                          Net
104
tt_51_3_sx_0[12]                  LUT4          I0        In      3.1                      
tt_51_3_sx_0[12]                  LUT4          O         Out     4.0
0.9          
tt_51_3_sx_0[12]                  Net
2  
y_shiftrotr_1_12.G_2918_sx_x0     LUT4          I2        In      4.0                      
y_shiftrotr_1_12.G_2918_sx_x0     LUT4          O         Out     4.8
0.8          
N_8013                            Net
1  
y_shiftrotr_1_12.G_2918_sx        MUXF5         I0        In      4.8                      
y_shiftrotr_1_12.G_2918_sx        MUXF5         O         Out     5.3
0.5          
y_shiftrotr_1_12.G_2918_sx        Net
1  
y_shiftrotr_1_12.G_2918           MUXF5         S         In      5.3                      
y_shiftrotr_1_12.G_2918           MUXF5         O         Out     6.6
1.3          
N_4614                            Net
2  
y_shiftrotr_1_12.G_2922_am        LUT3          I2        In      6.6                      
y_shiftrotr_1_12.G_2922_am        LUT3          O         Out     7.4
0.8          
N_6169                            Net
1  
y_shiftrotr_1_12.G_2922           MUXF5         I0        In      7.4                      
y_shiftrotr_1_12.G_2922           MUXF5         O         Out     7.9
0.5          
N_4618                            Net
1  
y_shiftrotr_1_12.G_2927           LUT4          I3        In      7.9                      
y_shiftrotr_1_12.G_2927           LUT4          O         Out     8.7
0.8          
N_4623                            Net
1  
y_shiftrotr_1_m[12]               LUT4          I2        In      8.7                      
y_shiftrotr_1_m[12]               LUT4          O         Out     9.5
0.8          
y_shiftrotr_1_m[12]               Net
1  
Y_iv_12.G_3859                    LUT4          I0        In      9.5                      
Y_iv_12.G_3859                    LUT4          O         Out     10.5
1.0          
N_5555                            Net
1  
Y_iv[12]                          MUXF5         S         In      10.5                     
Y_iv[12]                          MUXF5         O         Out     11.5
1.0          
Y_c[12]                           Net
1  
Y_obuf[12]                        OBUF_F_24     I         In      11.5                     
Y_obuf[12]                        OBUF_F_24     O         Out     15.0
3.5          
Y[12]                             Net
1  
Y[63:0]                           Port          Y[12]     In      15.0                     
===========================================================================================
This path has no setup requirement

A Critical Path with worst case slack = -9.3 ns:  

The start and the end point of this path are clocked by the System
Instance/Net                     Pin       Pin     Arrival     Delta
Fan
Name               Type          Name      Dir     Time        Delay
Out
----------------------------------------------------------------------------
                   Shuffle64     View                                       
B[63:0]            Port          B[2]      Out     0.0         0.0          
B[2]               Net                                                   1  
B_ibuf[2]          IBUF          I         In      0.0                      
B_ibuf[2]          IBUF          O         Out     0.9         0.9          
B_c[2]             Net                                                   3  
B_c_2[2]           BUF           I         In      0.9                      
B_c_2[2]           BUF           O         Out     3.1         2.2          
B_c_2[2]           Net
91 
tt_7_sx[2]         LUT2          I1        In      3.1                      
tt_7_sx[2]         LUT2          O         Out     3.9         0.8          
tt_7_sx[2]         Net                                                   1  
tt_7[2]            LUT4          I3        In      3.9                      
tt_7[2]            LUT4          O         Out     5.2         1.3          
tt[2]              Net                                                   8  
yy_9_58.G_3720     LUT4          I3        In      5.2                      
yy_9_58.G_3720     LUT4          O         Out     6.0         0.8          
N_5416             Net                                                   1  
yy_9_58.G_3722     LUT3          I0        In      6.0                      
yy_9_58.G_3722     LUT3          O         Out     7.0         1.0          
N_5418             Net                                                   1  
yy_9_58.G_3724     LUT4          I2        In      7.0                      
yy_9_58.G_3724     LUT4          O         Out     7.8         0.8          
N_5420             Net                                                   1  
yy_9_58.G_3732     LUT4          I0        In      7.8                      
yy_9_58.G_3732     LUT4          O         Out     8.7         0.9          
N_5428             Net                                                   2  
yy_9[58]           LUT4          I0        In      8.7                      
yy_9[58]           LUT4          O         Out     9.8         1.1          
yy_9[58]           Net                                                   4  
Y_0_iv_sx[26]      LUT4          I1        In      9.8                      
Y_0_iv_sx[26]      LUT4          O         Out     10.6        0.8          
Y_0_iv_sx[26]      Net                                                   1  
Y_0_iv[26]         LUT4          I3        In      10.6                     
Y_0_iv[26]         LUT4          O         Out     11.0        0.4          
Y_c[26]            Net                                                   1  
Y_obuf[26]         OBUF_F_24     I         In      11.0                     
Y_obuf[26]         OBUF_F_24     O         Out     14.5        3.5          
Y[26]              Net                          



=============================================================================
Mr. Kim Enkovaara   | kim.enkovaara@iki.fi | Microelectronic Riemannian
Vasamatie 1 C 16    | IRC: embo            | curved-space fault in
02630 Espoo         |                      | write-only file system

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