Re: Rep:[f-cpu] Hot issue : external LSU ?

["Christophe Avoinne" <christophe.avoinne@laposte.net>]

Well let's and see. For the moment we haven't even a uniprocessor working so
we should delay this issue until it comes necessary.

----- Original Message -----
From: "nico" <nicolas.boulay@ifrance.com>
To: <f-cpu@seul.org>
Sent: Sunday, September 01, 2002 1:07 PM
Subject: Re: Rep:[f-cpu] Hot issue : external LSU ?


> Imagine 32 node with Apache process&thread. In the worst case, you could
> go in infinite loop, no ?
>

No, because there would always one which succeeds. If one succeeds, the
others will have more chance to succeed too until all succeed. The laptime
spent between 'll' and 'sc' is so ridiculous short compared with the rest
that must be executed. Anyway, I see 'll/sc' as a way to do no blocking
synchronistation, but not the only one.

> If the bus is locked, yes. Maybe with split CAS cycle ? The destination
> of the load is locked during few cycle waiting for the conditionnal
> store. Or you define not a read-modify-write cycle but a true CAS cycle.
> The comparaison is maid by the controler (adresse of the load, data to
> be compare and the write). The return is just an ack.

Well a true CAS cycle would be more interesting. Such thing is possible ?

> > If you want only intra-cpu locking, you are still preventing the other
cpu
> > from normal load/store operation.
> >
>
> I don't like to differ inter and intra cpu process operation. Otherwise,
> 2 thread running on the same cpu will not have the same code as 2 thread
> running on 2 cpu. And that's baaaaaad !

No, you didn't understand me. Intra-cpu locking can be interesting if code
just need to be executed in a uni-processor environment. That's all.

Anyway, the uniprocessor wouldn't suffer from an external-LSU since it
doesn't need to be present (behaves as if no-dirty bit checking always
succeeds in that case) and you don't incur an io bus locking indeed.

The external-LSU behaves exactly as an internal-LSU but it is shared between
CPU. The only instant when you have a locktime is when several cpus tries to
 access meanwhile. But such a thing would happen for CAS too.

> The external LSU means a set/unset for each access and that is a cost
> for each memory access.

The external LSU is only accessed when a inter-cpu locking is involved and
is accessed as a cpu would access an internal LSU.

> I really don't like state in hardware, that's a lot of problem in the
> future : test, speed, speed up,...

State ? I'm not sure there is any state with 'll/sc'.

---

I believe Whygee and Michael R. prefer 'll/sc' instructions against CAS
instruction.

---

I need to know the real format of your CAS.

For me it should look something like  :

    before : three registers contain an expected value, a value address and
a new value
    after :  one register contains the read value before writing
or
    before : three registers contain an expected value, a value address and
a new value
    after :  one register contains a boolean value telling us if writing
succeeds.

Is such format possible with a CAS cycle ?

CAS2: geeek ! we need 6 registers instead of 3 ! of course we can decide to
use pair of registers ( rN', rN^1). But I feel it isn't feasible.




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