Re: gEDA-bug: [Bug 821618] Re: Very basic concatenated net support for verilognetlister

[Frank <821618@xxxxxxxxxxxxxxxxxx>]

Hi Peter,

It's been so long I don't remember which version, it would have been the 
current version as of the date of submission but I've been working with so 
many different tools and computers and linux versions I honestly don't 
recall. I'm putting together a digital IC design flow using open source 
tools and and am using gschem for schematic entry and needed to support 
bundles in verilog, if you've ever done FPGA or digital IC design you know 
how often we use bundles to create a bus to move things like control signals 
around.

I'll try to remember to use the git format in the future.

-Frank

-----Original Message----- 
From: Peter TB Brett
Sent: Sunday, December 11, 2011 3:51 AM
To: frank@xxxxxxxxxxxxxxxx
Subject: [Bug 821618] Re: Very basic concatenated net support for 
verilognetlister

Hi Frank - thanks for submitting this change, and sorry for not looking
at it sooner. What version of gEDA is this based on?

Thanks!

P.S. We usually prefer patches (preferably made with "git format-
patch"), because it's easier to see what's been changed.

** Changed in: geda
   Importance: Undecided => Medium

** Tags added: gnetlist

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https://bugs.launchpad.net/bugs/821618

Title:
  Very basic concatenated net support for verilog netlister

Status in GPL Electronic Design Automation tools:
  New

Bug description:
  I couldn't find a way to submit an updated netlister backend so
  figured this was the best path. I modified gnet-verilog.scm to support
  the basic verilog format concatenated net naming like {a,b,c[3:0]}.
  Attached is my updated gnet-verilog.scm.

To manage notifications about this bug go to:
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You received this bug notification because you are a member of gEDA Bug
Team, which is subscribed to gEDA.
https://bugs.launchpad.net/bugs/821618

Title:
  Very basic concatenated net support for verilog netlister

Status in GPL Electronic Design Automation tools:
  New

Bug description:
  I couldn't find a way to submit an updated netlister backend so
  figured this was the best path. I modified gnet-verilog.scm to support
  the basic verilog format concatenated net naming like {a,b,c[3:0]}.
  Attached is my updated gnet-verilog.scm.

To manage notifications about this bug go to:
https://bugs.launchpad.net/geda/+bug/821618/+subscriptions


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