gEDA-bug: [Bug 821618] Re: Very basic concatenated net support for verilog netlister

["gpleda.org commit robot" <821618@xxxxxxxxxxxxxxxxxx>]

Bug was fixed by a commit
git master commit 8741d194a6c2fa304d15123d398a9c3758169e6e
http://git.gpleda.org/?p=gaf.git;a=commit;h=8741d194a6c2fa304d15123d398a9c3758169e6e

commit 8741d194a6c2fa304d15123d398a9c3758169e6e
Author: Peter TB Brett <peter@xxxxxxxxxxxxx>
Commit: Peter TB Brett <peter@xxxxxxxxxxxxx>

    gnetlist: Add basic concatenated net support for verilog.
    
    Frank Thomson says: "I modified gnet-verilog.scm to support the basic
    verilog format concatenated net naming like {a,b,c[3:0]}."
    
    Closes-bug: lp-821618

** Changed in: geda
       Status: New => Fix Committed

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https://bugs.launchpad.net/bugs/821618

Title:
  Very basic concatenated net support for verilog netlister

Status in GPL Electronic Design Automation tools:
  Fix Committed

Bug description:
  I couldn't find a way to submit an updated netlister backend so
  figured this was the best path. I modified gnet-verilog.scm to support
  the basic verilog format concatenated net naming like {a,b,c[3:0]}.
  Attached is my updated gnet-verilog.scm.

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