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Re: gEDA-bug: gEDA-user: PCB: DRC does not correctly check pad clearance



On Feb 21 2011, Ineiev wrote:

On 2/19/11, Kai-Martin Knaak <kmk@xxxxxxxxxxxx> wrote:
I can confirm for fairly recent versions of pcb and pcb+gl.
In your example, DRC starts to complain at 7.1 mil. That is, 2 mil
too late. The discrepancy grows as the clearance grows. With an
11 mil gap I had to ask for 14.1 mil minimum distance to receive
DRC errors.

It looks like Bloat in IsLineInPolygon() should be doubled like in the
attachment.

Sounds about right - of this appears to fix the problem for the OP, please commit the fix ;)

This is awesome - more developers!!!

I'm trying to convince Martin Kupec to apply for commit access too - even if he prefers to get us to review stuff first before he pushes.

Best wishes,



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