gEDA-bug: [Bug 698847] Re: Advanced net selection

[Peter TB Brett <peter@xxxxxxxxxxxxx>]

It can often be useful for a net to have multiple names.  I have used
this before when I have an FPGA with eight IO banks, each with their own
IO voltage, and many VCCIO pins.  Connecting up the VCCIO pins is
easiest using a 'net=VCCIO<n>:...' attribute, and I did this and then
shorted the VCCIO<n> attribute to my 2.5V net elsewhere in the circuit.

This is a feature, not a bug.

** Changed in: geda
       Status: New => Won't Fix

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https://bugs.launchpad.net/bugs/698847

Title:
  Advanced net selection

Status in GPL Electronic Design Automation tools:
  Won't Fix

Bug description:
  Hallo Werner,

i've tested the behaviour of the ->(net-selection-mode "enabled_all") with the net_selection.sch.
(Test0, Test1, Test2 is working VERY well)
I've notice some confusing behaviour:
e.g. Test 3 in the middle of the net path:
There is a net connected to "bb1" on the one side and the same net with netname "bb2" on the other side.
What should the netlister do in this case?
Which net has the prioity?
I think this beh. should not be possible (see: https://sourceforge.net/tracker/?func=detail&aid=2031198&group_id=161080&atid=818426 ).
A phy. connected net should have the same name at each segment!?

In which case the user need multible netnames?

Cheers
Thomas




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