gEDA-bug: [ geda-Patches-1728708 ] fix bussed ports in Verilog netlists

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Patches item #1728708, was opened at 2007-05-30 19:56
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Category: None
Group: None
Status: Open
Resolution: None
Priority: 5
Private: No
Submitted By: Jeff Trull (jetrull)
Assigned to: Nobody/Anonymous (nobody)
Summary: fix bussed ports in Verilog netlists

Initial Comment:
If you have bussed I/O ports in your schematic you will see them declared multiple times in the output Verilog.  This is because the Verilog netlister iterates over all physical wires in the netlist when it outputs ports.  For example, you might have

module whatever (
      B ,
      B
);

input [1:0] B;
input [1:0] B;

when B should only be declared once in each place.

This patch filters out repeated ports before they are processed by the main output functions.




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You can respond by visiting: 
https://sourceforge.net/tracker/?func=detail&atid=818428&aid=1728708&group_id=161080


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