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gEDA-cvs: Commit by: mike



CVSROOT:	/home/cvspsrv/cvsroot
Module name:	eda
Changes by:	mike	04/12/01 15:16:51

Modified files:
	geda/devel/gnetlist/scheme: gnet-verilog.scm 

Log message:
Netlisting with symbols having pin-names like `A[15:0]' generated
Verilog with syntax errors.  It was necessary to remove the additional
brackets.
Patched verilog:display-pin to extract the netname from the symbol pin
name, thus filtering out bit range expressions.