[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]
gEDA-cvs: Commit by: mike
- To: geda-cvs@xxxxxxxx
- Subject: gEDA-cvs: Commit by: mike
- From: SEUL CVS pserver <cvspsrv@xxxxxxxx>
- Date: Mon, 20 Dec 2004 14:30:49 -0500 (EST)
- Delivered-to: archiver@seul.org
- Delivered-to: geda-cvs-outgoing@seul.org
- Delivered-to: geda-cvs@seul.org
- Delivery-date: Mon, 20 Dec 2004 14:31:13 -0500
- Mail-copies-to: never
- Reply-to: geda-cvs@xxxxxxxx
- Sender: owner-geda-cvs@xxxxxxxx
CVSROOT: /home/cvspsrv/cvsroot
Module name: eda
Changes by: mike 04/12/20 14:30:49
Modified files:
geda/devel/gnetlist/scheme: gnet-verilog.scm
Log message:
Added logic to output wire widths on the input, output, and inout module port
declarations. The logic usess the same printing routines as are used in the
wire printing routines.
Further optimization is possible by re-writing the verilog:get-nets routine
so that it is only called once at the beginning, instead of every time a net
needs to be looked up.