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gEDA-cvs: gaf.git: branch: master updated (1.7.0-20110116-78-g4d566fc)
The branch, master has been updated
via 4d566fcde7d57daeac1ad5629b5bb1baacc3a030 (commit)
via 43c59a0c55c94a499aea448785b62ab1242e8da7 (commit)
from 5a5fe91b382be44b07f02ca229d751a7fb225838 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
=========
Summary
=========
.../outputs/gsch2pcb/JD_Include_nomunge-output.net | 11 +++++++++
.../common/outputs/gsch2pcb/JD_Sort-output.net | 11 +++++++++
.../outputs/gsch2pcb/JD_Sort_nomunge-output.net | 11 +++++++++
.../outputs/gsch2pcb/SlottedOpamps-output.net | 1 +
.../common/outputs/gsch2pcb/TwoStageAmp-output.net | 23 ++++++++++++++++++++
.../gsch2pcb/TwoStageAmp_Include-output.net | 23 ++++++++++++++++++++
.../outputs/gsch2pcb/TwoStageAmp_Sort-output.net | 23 ++++++++++++++++++++
.../common/outputs/gsch2pcb/cascade-output.net | 8 +++++++
.../common/outputs/gsch2pcb/multiequal-output.net | 3 ++
.../common/outputs/gsch2pcb/netattrib-output.net | 4 +++
.../common/outputs/gsch2pcb/powersupply-output.net | 12 ++++++++++
.../common/outputs/gsch2pcb/singlenet-output.net | 1 +
.../outputs/gsch2pcb/stack-torture-output.net | 1 +
13 files changed, 132 insertions(+), 0 deletions(-)
=================
Commit Messages
=================
commit 4d566fcde7d57daeac1ad5629b5bb1baacc3a030
Author: Peter TB Brett <peter@xxxxxxxxxxxxx>
Commit: Peter TB Brett <peter@xxxxxxxxxxxxx>
Update gsch2pcb backend golden files.
gsch2pcb backend output was altered in commit dc5914e6538a, but the
testsuite golden files were not updated.
Correct version of 5a5fe91b382b.
:100644 100644 9c073e0... 9b1f2b5... M gnetlist/tests/common/outputs/gsch2pcb/JD-output.net
:100644 100644 9c073e0... 9b1f2b5... M gnetlist/tests/common/outputs/gsch2pcb/JD_Include-output.net
:100644 100644 9c073e0... 9b1f2b5... M gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge-output.net
:100644 100644 9c073e0... 9b1f2b5... M gnetlist/tests/common/outputs/gsch2pcb/JD_Sort-output.net
:100644 100644 9c073e0... 9b1f2b5... M gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge-output.net
:100644 100644 9c073e0... 9b1f2b5... M gnetlist/tests/common/outputs/gsch2pcb/JD_nomunge-output.net
:100644 100644 d8ef4dc... 8d11e4c... M gnetlist/tests/common/outputs/gsch2pcb/SlottedOpamps-output.net
:100644 100644 94f9896... 8756898... M gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp-output.net
:100644 100644 94f9896... 8756898... M gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include-output.net
:100644 100644 94f9896... 8756898... M gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort-output.net
:100644 100644 3f5c511... c39e2bd... M gnetlist/tests/common/outputs/gsch2pcb/cascade-output.net
:100644 100644 2bdf919... ae1ff5d... M gnetlist/tests/common/outputs/gsch2pcb/multiequal-output.net
:100644 100644 c40fb5b... 1439c58... M gnetlist/tests/common/outputs/gsch2pcb/netattrib-output.net
:100644 100644 3804abe... 851522b... M gnetlist/tests/common/outputs/gsch2pcb/powersupply-output.net
:100644 100644 42b0d58... 28e9543... M gnetlist/tests/common/outputs/gsch2pcb/singlenet-output.net
:100644 100644 79a8e98... e0f4b46... M gnetlist/tests/common/outputs/gsch2pcb/stack-torture-output.net
commit 43c59a0c55c94a499aea448785b62ab1242e8da7
Author: Peter TB Brett <peter@xxxxxxxxxxxxx>
Commit: Peter TB Brett <peter@xxxxxxxxxxxxx>
Revert "Update gsch2pcb backend golden files."
This reverts commit 5a5fe91b382be44b07f02ca229d751a7fb225838.
:100644 100644 9b1f2b5... 9c073e0... M gnetlist/tests/common/outputs/gsch2pcb/JD-output.net
:100644 100644 9b1f2b5... 9c073e0... M gnetlist/tests/common/outputs/gsch2pcb/JD_Include-output.net
:100644 100644 ee6d5fa... 9c073e0... M gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge-output.net
:100644 100644 ee6d5fa... 9c073e0... M gnetlist/tests/common/outputs/gsch2pcb/JD_Sort-output.net
:100644 100644 ee6d5fa... 9c073e0... M gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge-output.net
:100644 100644 9b1f2b5... 9c073e0... M gnetlist/tests/common/outputs/gsch2pcb/JD_nomunge-output.net
:100644 100644 ee6d5fa... d8ef4dc... M gnetlist/tests/common/outputs/gsch2pcb/SlottedOpamps-output.net
:100644 100644 ee6d5fa... 94f9896... M gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp-output.net
:100644 100644 ee6d5fa... 94f9896... M gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include-output.net
:100644 100644 ee6d5fa... 94f9896... M gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort-output.net
:100644 100644 ee6d5fa... 3f5c511... M gnetlist/tests/common/outputs/gsch2pcb/cascade-output.net
:100644 100644 ee6d5fa... 2bdf919... M gnetlist/tests/common/outputs/gsch2pcb/multiequal-output.net
:100644 100644 ee6d5fa... c40fb5b... M gnetlist/tests/common/outputs/gsch2pcb/netattrib-output.net
:100644 100644 ee6d5fa... 3804abe... M gnetlist/tests/common/outputs/gsch2pcb/powersupply-output.net
:100644 100644 ee6d5fa... 42b0d58... M gnetlist/tests/common/outputs/gsch2pcb/singlenet-output.net
:100644 100644 ee6d5fa... 79a8e98... M gnetlist/tests/common/outputs/gsch2pcb/stack-torture-output.net
=========
Changes
=========
commit 4d566fcde7d57daeac1ad5629b5bb1baacc3a030
Author: Peter TB Brett <peter@xxxxxxxxxxxxx>
Commit: Peter TB Brett <peter@xxxxxxxxxxxxx>
Update gsch2pcb backend golden files.
gsch2pcb backend output was altered in commit dc5914e6538a, but the
testsuite golden files were not updated.
Correct version of 5a5fe91b382b.
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD-output.net
index 9c073e0..9b1f2b5 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD-output.net
@@ -8,7 +8,7 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2,s:3:4:5:6:7:8")
+Groups("1,c:2:3:4:5:6,s:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_unknown(unknown,A1,unknown)
PKG_unknown(unknown,Cm,20p)
@@ -21,28 +21,28 @@ PKG_unknown(unknown,Rt,1k)
PKG_unknown(unknown,Rb,5.6k)
PKG_unknown(unknown,M1,unknown)
PKG_unknown(unknown,X1,unknown)
-Layer(1 "component")
+Layer(1 "top")
(
)
-Layer(2 "solder")
+Layer(2 "ground")
(
)
-Layer(3 "outline")
+Layer(3 "signal2")
(
)
-Layer(4 "GND")
+Layer(4 "signal3")
(
)
Layer(5 "power")
(
)
-Layer(6 "signal1")
+Layer(6 "bottom")
(
)
-Layer(7 "signal2")
+Layer(7 "outline")
(
)
-Layer(8 "signal3")
+Layer(8 "spare")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Include-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include-output.net
index 9c073e0..9b1f2b5 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include-output.net
@@ -8,7 +8,7 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2,s:3:4:5:6:7:8")
+Groups("1,c:2:3:4:5:6,s:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_unknown(unknown,A1,unknown)
PKG_unknown(unknown,Cm,20p)
@@ -21,28 +21,28 @@ PKG_unknown(unknown,Rt,1k)
PKG_unknown(unknown,Rb,5.6k)
PKG_unknown(unknown,M1,unknown)
PKG_unknown(unknown,X1,unknown)
-Layer(1 "component")
+Layer(1 "top")
(
)
-Layer(2 "solder")
+Layer(2 "ground")
(
)
-Layer(3 "outline")
+Layer(3 "signal2")
(
)
-Layer(4 "GND")
+Layer(4 "signal3")
(
)
Layer(5 "power")
(
)
-Layer(6 "signal1")
+Layer(6 "bottom")
(
)
-Layer(7 "signal2")
+Layer(7 "outline")
(
)
-Layer(8 "signal3")
+Layer(8 "spare")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge-output.net
index 9c073e0..9b1f2b5 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge-output.net
@@ -8,7 +8,7 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2,s:3:4:5:6:7:8")
+Groups("1,c:2:3:4:5:6,s:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_unknown(unknown,A1,unknown)
PKG_unknown(unknown,Cm,20p)
@@ -21,28 +21,28 @@ PKG_unknown(unknown,Rt,1k)
PKG_unknown(unknown,Rb,5.6k)
PKG_unknown(unknown,M1,unknown)
PKG_unknown(unknown,X1,unknown)
-Layer(1 "component")
+Layer(1 "top")
(
)
-Layer(2 "solder")
+Layer(2 "ground")
(
)
-Layer(3 "outline")
+Layer(3 "signal2")
(
)
-Layer(4 "GND")
+Layer(4 "signal3")
(
)
Layer(5 "power")
(
)
-Layer(6 "signal1")
+Layer(6 "bottom")
(
)
-Layer(7 "signal2")
+Layer(7 "outline")
(
)
-Layer(8 "signal3")
+Layer(8 "spare")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort-output.net
index 9c073e0..9b1f2b5 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort-output.net
@@ -8,7 +8,7 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2,s:3:4:5:6:7:8")
+Groups("1,c:2:3:4:5:6,s:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_unknown(unknown,A1,unknown)
PKG_unknown(unknown,Cm,20p)
@@ -21,28 +21,28 @@ PKG_unknown(unknown,Rt,1k)
PKG_unknown(unknown,Rb,5.6k)
PKG_unknown(unknown,M1,unknown)
PKG_unknown(unknown,X1,unknown)
-Layer(1 "component")
+Layer(1 "top")
(
)
-Layer(2 "solder")
+Layer(2 "ground")
(
)
-Layer(3 "outline")
+Layer(3 "signal2")
(
)
-Layer(4 "GND")
+Layer(4 "signal3")
(
)
Layer(5 "power")
(
)
-Layer(6 "signal1")
+Layer(6 "bottom")
(
)
-Layer(7 "signal2")
+Layer(7 "outline")
(
)
-Layer(8 "signal3")
+Layer(8 "spare")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge-output.net
index 9c073e0..9b1f2b5 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge-output.net
@@ -8,7 +8,7 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2,s:3:4:5:6:7:8")
+Groups("1,c:2:3:4:5:6,s:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_unknown(unknown,A1,unknown)
PKG_unknown(unknown,Cm,20p)
@@ -21,28 +21,28 @@ PKG_unknown(unknown,Rt,1k)
PKG_unknown(unknown,Rb,5.6k)
PKG_unknown(unknown,M1,unknown)
PKG_unknown(unknown,X1,unknown)
-Layer(1 "component")
+Layer(1 "top")
(
)
-Layer(2 "solder")
+Layer(2 "ground")
(
)
-Layer(3 "outline")
+Layer(3 "signal2")
(
)
-Layer(4 "GND")
+Layer(4 "signal3")
(
)
Layer(5 "power")
(
)
-Layer(6 "signal1")
+Layer(6 "bottom")
(
)
-Layer(7 "signal2")
+Layer(7 "outline")
(
)
-Layer(8 "signal3")
+Layer(8 "spare")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_nomunge-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_nomunge-output.net
index 9c073e0..9b1f2b5 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_nomunge-output.net
@@ -8,7 +8,7 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2,s:3:4:5:6:7:8")
+Groups("1,c:2:3:4:5:6,s:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_unknown(unknown,A1,unknown)
PKG_unknown(unknown,Cm,20p)
@@ -21,28 +21,28 @@ PKG_unknown(unknown,Rt,1k)
PKG_unknown(unknown,Rb,5.6k)
PKG_unknown(unknown,M1,unknown)
PKG_unknown(unknown,X1,unknown)
-Layer(1 "component")
+Layer(1 "top")
(
)
-Layer(2 "solder")
+Layer(2 "ground")
(
)
-Layer(3 "outline")
+Layer(3 "signal2")
(
)
-Layer(4 "GND")
+Layer(4 "signal3")
(
)
Layer(5 "power")
(
)
-Layer(6 "signal1")
+Layer(6 "bottom")
(
)
-Layer(7 "signal2")
+Layer(7 "outline")
(
)
-Layer(8 "signal3")
+Layer(8 "spare")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/gsch2pcb/SlottedOpamps-output.net
index d8ef4dc..8d11e4c 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/SlottedOpamps-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/SlottedOpamps-output.net
@@ -8,31 +8,31 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2,s:3:4:5:6:7:8")
+Groups("1,c:2:3:4:5:6,s:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_unknown(unknown,U1,unknown)
-Layer(1 "component")
+Layer(1 "top")
(
)
-Layer(2 "solder")
+Layer(2 "ground")
(
)
-Layer(3 "outline")
+Layer(3 "signal2")
(
)
-Layer(4 "GND")
+Layer(4 "signal3")
(
)
Layer(5 "power")
(
)
-Layer(6 "signal1")
+Layer(6 "bottom")
(
)
-Layer(7 "signal2")
+Layer(7 "outline")
(
)
-Layer(8 "signal3")
+Layer(8 "spare")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp-output.net
index 94f9896..8756898 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp-output.net
@@ -8,7 +8,7 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2,s:3:4:5:6:7:8")
+Groups("1,c:2:3:4:5:6,s:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_unknown(unknown,C2,2.2uF)
PKG_unknown(unknown,R4,2.8K)
@@ -33,28 +33,28 @@ PKG_unknown(unknown,R2,2K)
PKG_unknown(unknown,R1,28K)
PKG_unknown(unknown,R5,10)
PKG_unknown(unknown,Q1,unknown)
-Layer(1 "component")
+Layer(1 "top")
(
)
-Layer(2 "solder")
+Layer(2 "ground")
(
)
-Layer(3 "outline")
+Layer(3 "signal2")
(
)
-Layer(4 "GND")
+Layer(4 "signal3")
(
)
Layer(5 "power")
(
)
-Layer(6 "signal1")
+Layer(6 "bottom")
(
)
-Layer(7 "signal2")
+Layer(7 "outline")
(
)
-Layer(8 "signal3")
+Layer(8 "spare")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include-output.net
index 94f9896..8756898 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include-output.net
@@ -8,7 +8,7 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2,s:3:4:5:6:7:8")
+Groups("1,c:2:3:4:5:6,s:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_unknown(unknown,C2,2.2uF)
PKG_unknown(unknown,R4,2.8K)
@@ -33,28 +33,28 @@ PKG_unknown(unknown,R2,2K)
PKG_unknown(unknown,R1,28K)
PKG_unknown(unknown,R5,10)
PKG_unknown(unknown,Q1,unknown)
-Layer(1 "component")
+Layer(1 "top")
(
)
-Layer(2 "solder")
+Layer(2 "ground")
(
)
-Layer(3 "outline")
+Layer(3 "signal2")
(
)
-Layer(4 "GND")
+Layer(4 "signal3")
(
)
Layer(5 "power")
(
)
-Layer(6 "signal1")
+Layer(6 "bottom")
(
)
-Layer(7 "signal2")
+Layer(7 "outline")
(
)
-Layer(8 "signal3")
+Layer(8 "spare")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort-output.net
index 94f9896..8756898 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort-output.net
@@ -8,7 +8,7 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2,s:3:4:5:6:7:8")
+Groups("1,c:2:3:4:5:6,s:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_unknown(unknown,C2,2.2uF)
PKG_unknown(unknown,R4,2.8K)
@@ -33,28 +33,28 @@ PKG_unknown(unknown,R2,2K)
PKG_unknown(unknown,R1,28K)
PKG_unknown(unknown,R5,10)
PKG_unknown(unknown,Q1,unknown)
-Layer(1 "component")
+Layer(1 "top")
(
)
-Layer(2 "solder")
+Layer(2 "ground")
(
)
-Layer(3 "outline")
+Layer(3 "signal2")
(
)
-Layer(4 "GND")
+Layer(4 "signal3")
(
)
Layer(5 "power")
(
)
-Layer(6 "signal1")
+Layer(6 "bottom")
(
)
-Layer(7 "signal2")
+Layer(7 "outline")
(
)
-Layer(8 "signal3")
+Layer(8 "spare")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/cascade-output.net b/gnetlist/tests/common/outputs/gsch2pcb/cascade-output.net
index 3f5c511..c39e2bd 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/cascade-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/cascade-output.net
@@ -8,7 +8,7 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2,s:3:4:5:6:7:8")
+Groups("1,c:2:3:4:5:6,s:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_none(none,AMP2,unknown)
PKG_none(none,T1,unknown)
@@ -18,28 +18,28 @@ PKG_none(none,DEF1,unknown)
PKG_none(none,AMP1,unknown)
PKG_none(none,SOURCE,unknown)
PKG_unknown(unknown,DEFAULTS,unknown)
-Layer(1 "component")
+Layer(1 "top")
(
)
-Layer(2 "solder")
+Layer(2 "ground")
(
)
-Layer(3 "outline")
+Layer(3 "signal2")
(
)
-Layer(4 "GND")
+Layer(4 "signal3")
(
)
Layer(5 "power")
(
)
-Layer(6 "signal1")
+Layer(6 "bottom")
(
)
-Layer(7 "signal2")
+Layer(7 "outline")
(
)
-Layer(8 "signal3")
+Layer(8 "spare")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/multiequal-output.net b/gnetlist/tests/common/outputs/gsch2pcb/multiequal-output.net
index 2bdf919..ae1ff5d 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/multiequal-output.net
@@ -8,33 +8,33 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2,s:3:4:5:6:7:8")
+Groups("1,c:2:3:4:5:6,s:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_none(none,V1,DC 1V)
PKG_unknown(unknown,R1,20)
PKG_unknown(unknown,A1,abotol=1e-11)
-Layer(1 "component")
+Layer(1 "top")
(
)
-Layer(2 "solder")
+Layer(2 "ground")
(
)
-Layer(3 "outline")
+Layer(3 "signal2")
(
)
-Layer(4 "GND")
+Layer(4 "signal3")
(
)
Layer(5 "power")
(
)
-Layer(6 "signal1")
+Layer(6 "bottom")
(
)
-Layer(7 "signal2")
+Layer(7 "outline")
(
)
-Layer(8 "signal3")
+Layer(8 "spare")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/netattrib-output.net b/gnetlist/tests/common/outputs/gsch2pcb/netattrib-output.net
index c40fb5b..1439c58 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/netattrib-output.net
@@ -8,34 +8,34 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2,s:3:4:5:6:7:8")
+Groups("1,c:2:3:4:5:6,s:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_unknown(unknown,F1,unknown)
PKG_DIP14(DIP14,U300,unknown)
PKG_DIP14(DIP14,U200,unknown)
PKG_DIP14(DIP14,U100,unknown)
-Layer(1 "component")
+Layer(1 "top")
(
)
-Layer(2 "solder")
+Layer(2 "ground")
(
)
-Layer(3 "outline")
+Layer(3 "signal2")
(
)
-Layer(4 "GND")
+Layer(4 "signal3")
(
)
Layer(5 "power")
(
)
-Layer(6 "signal1")
+Layer(6 "bottom")
(
)
-Layer(7 "signal2")
+Layer(7 "outline")
(
)
-Layer(8 "signal3")
+Layer(8 "spare")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/powersupply-output.net b/gnetlist/tests/common/outputs/gsch2pcb/powersupply-output.net
index 3804abe..851522b 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/powersupply-output.net
@@ -8,7 +8,7 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2,s:3:4:5:6:7:8")
+Groups("1,c:2:3:4:5:6,s:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_unknown(unknown,U2,unknown)
PKG_unknown(unknown,C4,1uf)
@@ -22,28 +22,28 @@ PKG_unknown(unknown,CONN1,unknown)
PKG_unknown(unknown,T1,unknown)
PKG_unknown(unknown,F1,unknown)
PKG_unknown(unknown,U1,unknown)
-Layer(1 "component")
+Layer(1 "top")
(
)
-Layer(2 "solder")
+Layer(2 "ground")
(
)
-Layer(3 "outline")
+Layer(3 "signal2")
(
)
-Layer(4 "GND")
+Layer(4 "signal3")
(
)
Layer(5 "power")
(
)
-Layer(6 "signal1")
+Layer(6 "bottom")
(
)
-Layer(7 "signal2")
+Layer(7 "outline")
(
)
-Layer(8 "signal3")
+Layer(8 "spare")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/singlenet-output.net b/gnetlist/tests/common/outputs/gsch2pcb/singlenet-output.net
index 42b0d58..28e9543 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/singlenet-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/singlenet-output.net
@@ -8,31 +8,31 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2,s:3:4:5:6:7:8")
+Groups("1,c:2:3:4:5:6,s:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_DIP14(DIP14,U100,unknown)
-Layer(1 "component")
+Layer(1 "top")
(
)
-Layer(2 "solder")
+Layer(2 "ground")
(
)
-Layer(3 "outline")
+Layer(3 "signal2")
(
)
-Layer(4 "GND")
+Layer(4 "signal3")
(
)
Layer(5 "power")
(
)
-Layer(6 "signal1")
+Layer(6 "bottom")
(
)
-Layer(7 "signal2")
+Layer(7 "outline")
(
)
-Layer(8 "signal3")
+Layer(8 "spare")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/stack-torture-output.net b/gnetlist/tests/common/outputs/gsch2pcb/stack-torture-output.net
index 79a8e98..e0f4b46 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/stack-torture-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/stack-torture-output.net
@@ -8,31 +8,31 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2,s:3:4:5:6:7:8")
+Groups("1,c:2:3:4:5:6,s:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_unknown(unknown,C?,unknown)
-Layer(1 "component")
+Layer(1 "top")
(
)
-Layer(2 "solder")
+Layer(2 "ground")
(
)
-Layer(3 "outline")
+Layer(3 "signal2")
(
)
-Layer(4 "GND")
+Layer(4 "signal3")
(
)
Layer(5 "power")
(
)
-Layer(6 "signal1")
+Layer(6 "bottom")
(
)
-Layer(7 "signal2")
+Layer(7 "outline")
(
)
-Layer(8 "signal3")
+Layer(8 "spare")
(
)
Layer(9 "silk")
commit 43c59a0c55c94a499aea448785b62ab1242e8da7
Author: Peter TB Brett <peter@xxxxxxxxxxxxx>
Commit: Peter TB Brett <peter@xxxxxxxxxxxxx>
Revert "Update gsch2pcb backend golden files."
This reverts commit 5a5fe91b382be44b07f02ca229d751a7fb225838.
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD-output.net
index 9b1f2b5..9c073e0 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD-output.net
@@ -8,7 +8,7 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2:3:4:5:6,s:7:8")
+Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_unknown(unknown,A1,unknown)
PKG_unknown(unknown,Cm,20p)
@@ -21,28 +21,28 @@ PKG_unknown(unknown,Rt,1k)
PKG_unknown(unknown,Rb,5.6k)
PKG_unknown(unknown,M1,unknown)
PKG_unknown(unknown,X1,unknown)
-Layer(1 "top")
+Layer(1 "component")
(
)
-Layer(2 "ground")
+Layer(2 "solder")
(
)
-Layer(3 "signal2")
+Layer(3 "outline")
(
)
-Layer(4 "signal3")
+Layer(4 "GND")
(
)
Layer(5 "power")
(
)
-Layer(6 "bottom")
+Layer(6 "signal1")
(
)
-Layer(7 "outline")
+Layer(7 "signal2")
(
)
-Layer(8 "spare")
+Layer(8 "signal3")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Include-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include-output.net
index 9b1f2b5..9c073e0 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include-output.net
@@ -8,7 +8,7 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2:3:4:5:6,s:7:8")
+Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_unknown(unknown,A1,unknown)
PKG_unknown(unknown,Cm,20p)
@@ -21,28 +21,28 @@ PKG_unknown(unknown,Rt,1k)
PKG_unknown(unknown,Rb,5.6k)
PKG_unknown(unknown,M1,unknown)
PKG_unknown(unknown,X1,unknown)
-Layer(1 "top")
+Layer(1 "component")
(
)
-Layer(2 "ground")
+Layer(2 "solder")
(
)
-Layer(3 "signal2")
+Layer(3 "outline")
(
)
-Layer(4 "signal3")
+Layer(4 "GND")
(
)
Layer(5 "power")
(
)
-Layer(6 "bottom")
+Layer(6 "signal1")
(
)
-Layer(7 "outline")
+Layer(7 "signal2")
(
)
-Layer(8 "spare")
+Layer(8 "signal3")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge-output.net
index ee6d5fa..9c073e0 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge-output.net
@@ -8,30 +8,41 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2:3:4:5:6,s:7:8")
+Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-Layer(1 "top")
+PKG_unknown(unknown,A1,unknown)
+PKG_unknown(unknown,Cm,20p)
+PKG_unknown(unknown,Cp,20p)
+PKG_unknown(unknown,Rlp,1meg)
+PKG_unknown(unknown,Rlm,500k)
+PKG_none(none,Vdd,DC 3.3V)
+PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+PKG_unknown(unknown,Rt,1k)
+PKG_unknown(unknown,Rb,5.6k)
+PKG_unknown(unknown,M1,unknown)
+PKG_unknown(unknown,X1,unknown)
+Layer(1 "component")
(
)
-Layer(2 "ground")
+Layer(2 "solder")
(
)
-Layer(3 "signal2")
+Layer(3 "outline")
(
)
-Layer(4 "signal3")
+Layer(4 "GND")
(
)
Layer(5 "power")
(
)
-Layer(6 "bottom")
+Layer(6 "signal1")
(
)
-Layer(7 "outline")
+Layer(7 "signal2")
(
)
-Layer(8 "spare")
+Layer(8 "signal3")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort-output.net
index ee6d5fa..9c073e0 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort-output.net
@@ -8,30 +8,41 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2:3:4:5:6,s:7:8")
+Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-Layer(1 "top")
+PKG_unknown(unknown,A1,unknown)
+PKG_unknown(unknown,Cm,20p)
+PKG_unknown(unknown,Cp,20p)
+PKG_unknown(unknown,Rlp,1meg)
+PKG_unknown(unknown,Rlm,500k)
+PKG_none(none,Vdd,DC 3.3V)
+PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+PKG_unknown(unknown,Rt,1k)
+PKG_unknown(unknown,Rb,5.6k)
+PKG_unknown(unknown,M1,unknown)
+PKG_unknown(unknown,X1,unknown)
+Layer(1 "component")
(
)
-Layer(2 "ground")
+Layer(2 "solder")
(
)
-Layer(3 "signal2")
+Layer(3 "outline")
(
)
-Layer(4 "signal3")
+Layer(4 "GND")
(
)
Layer(5 "power")
(
)
-Layer(6 "bottom")
+Layer(6 "signal1")
(
)
-Layer(7 "outline")
+Layer(7 "signal2")
(
)
-Layer(8 "spare")
+Layer(8 "signal3")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge-output.net
index ee6d5fa..9c073e0 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge-output.net
@@ -8,30 +8,41 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2:3:4:5:6,s:7:8")
+Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-Layer(1 "top")
+PKG_unknown(unknown,A1,unknown)
+PKG_unknown(unknown,Cm,20p)
+PKG_unknown(unknown,Cp,20p)
+PKG_unknown(unknown,Rlp,1meg)
+PKG_unknown(unknown,Rlm,500k)
+PKG_none(none,Vdd,DC 3.3V)
+PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+PKG_unknown(unknown,Rt,1k)
+PKG_unknown(unknown,Rb,5.6k)
+PKG_unknown(unknown,M1,unknown)
+PKG_unknown(unknown,X1,unknown)
+Layer(1 "component")
(
)
-Layer(2 "ground")
+Layer(2 "solder")
(
)
-Layer(3 "signal2")
+Layer(3 "outline")
(
)
-Layer(4 "signal3")
+Layer(4 "GND")
(
)
Layer(5 "power")
(
)
-Layer(6 "bottom")
+Layer(6 "signal1")
(
)
-Layer(7 "outline")
+Layer(7 "signal2")
(
)
-Layer(8 "spare")
+Layer(8 "signal3")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_nomunge-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_nomunge-output.net
index 9b1f2b5..9c073e0 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_nomunge-output.net
@@ -8,7 +8,7 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2:3:4:5:6,s:7:8")
+Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_unknown(unknown,A1,unknown)
PKG_unknown(unknown,Cm,20p)
@@ -21,28 +21,28 @@ PKG_unknown(unknown,Rt,1k)
PKG_unknown(unknown,Rb,5.6k)
PKG_unknown(unknown,M1,unknown)
PKG_unknown(unknown,X1,unknown)
-Layer(1 "top")
+Layer(1 "component")
(
)
-Layer(2 "ground")
+Layer(2 "solder")
(
)
-Layer(3 "signal2")
+Layer(3 "outline")
(
)
-Layer(4 "signal3")
+Layer(4 "GND")
(
)
Layer(5 "power")
(
)
-Layer(6 "bottom")
+Layer(6 "signal1")
(
)
-Layer(7 "outline")
+Layer(7 "signal2")
(
)
-Layer(8 "spare")
+Layer(8 "signal3")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/gsch2pcb/SlottedOpamps-output.net
index ee6d5fa..d8ef4dc 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/SlottedOpamps-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/SlottedOpamps-output.net
@@ -8,30 +8,31 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2:3:4:5:6,s:7:8")
+Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-Layer(1 "top")
+PKG_unknown(unknown,U1,unknown)
+Layer(1 "component")
(
)
-Layer(2 "ground")
+Layer(2 "solder")
(
)
-Layer(3 "signal2")
+Layer(3 "outline")
(
)
-Layer(4 "signal3")
+Layer(4 "GND")
(
)
Layer(5 "power")
(
)
-Layer(6 "bottom")
+Layer(6 "signal1")
(
)
-Layer(7 "outline")
+Layer(7 "signal2")
(
)
-Layer(8 "spare")
+Layer(8 "signal3")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp-output.net
index ee6d5fa..94f9896 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp-output.net
@@ -8,30 +8,53 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2:3:4:5:6,s:7:8")
+Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-Layer(1 "top")
+PKG_unknown(unknown,C2,2.2uF)
+PKG_unknown(unknown,R4,2.8K)
+PKG_unknown(unknown,R3,28K)
+PKG_unknown(unknown,R8,1)
+PKG_unknown(unknown,CE2,1pF)
+PKG_unknown(unknown,RE2,100)
+PKG_unknown(unknown,RC1,3.3K)
+PKG_unknown(unknown,Q2,unknown)
+PKG_unknown(unknown,C1,2.2uF)
+PKG_unknown(unknown,A3,.options TEMP=25)
+PKG_unknown(unknown,A2,unknown)
+PKG_unknown(unknown,A1,unknown)
+PKG_none(none,VCC,DC 15V)
+PKG_none(none,Vinput,DC 1.6V AC 10MV SIN(0 1MV 1KHZ))
+PKG_unknown(unknown,CE1,1pF)
+PKG_unknown(unknown,Cout,2.2uF)
+PKG_unknown(unknown,RL,100K)
+PKG_unknown(unknown,RC2,1K)
+PKG_unknown(unknown,RE1,100)
+PKG_unknown(unknown,R2,2K)
+PKG_unknown(unknown,R1,28K)
+PKG_unknown(unknown,R5,10)
+PKG_unknown(unknown,Q1,unknown)
+Layer(1 "component")
(
)
-Layer(2 "ground")
+Layer(2 "solder")
(
)
-Layer(3 "signal2")
+Layer(3 "outline")
(
)
-Layer(4 "signal3")
+Layer(4 "GND")
(
)
Layer(5 "power")
(
)
-Layer(6 "bottom")
+Layer(6 "signal1")
(
)
-Layer(7 "outline")
+Layer(7 "signal2")
(
)
-Layer(8 "spare")
+Layer(8 "signal3")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include-output.net
index ee6d5fa..94f9896 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include-output.net
@@ -8,30 +8,53 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2:3:4:5:6,s:7:8")
+Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-Layer(1 "top")
+PKG_unknown(unknown,C2,2.2uF)
+PKG_unknown(unknown,R4,2.8K)
+PKG_unknown(unknown,R3,28K)
+PKG_unknown(unknown,R8,1)
+PKG_unknown(unknown,CE2,1pF)
+PKG_unknown(unknown,RE2,100)
+PKG_unknown(unknown,RC1,3.3K)
+PKG_unknown(unknown,Q2,unknown)
+PKG_unknown(unknown,C1,2.2uF)
+PKG_unknown(unknown,A3,.options TEMP=25)
+PKG_unknown(unknown,A2,unknown)
+PKG_unknown(unknown,A1,unknown)
+PKG_none(none,VCC,DC 15V)
+PKG_none(none,Vinput,DC 1.6V AC 10MV SIN(0 1MV 1KHZ))
+PKG_unknown(unknown,CE1,1pF)
+PKG_unknown(unknown,Cout,2.2uF)
+PKG_unknown(unknown,RL,100K)
+PKG_unknown(unknown,RC2,1K)
+PKG_unknown(unknown,RE1,100)
+PKG_unknown(unknown,R2,2K)
+PKG_unknown(unknown,R1,28K)
+PKG_unknown(unknown,R5,10)
+PKG_unknown(unknown,Q1,unknown)
+Layer(1 "component")
(
)
-Layer(2 "ground")
+Layer(2 "solder")
(
)
-Layer(3 "signal2")
+Layer(3 "outline")
(
)
-Layer(4 "signal3")
+Layer(4 "GND")
(
)
Layer(5 "power")
(
)
-Layer(6 "bottom")
+Layer(6 "signal1")
(
)
-Layer(7 "outline")
+Layer(7 "signal2")
(
)
-Layer(8 "spare")
+Layer(8 "signal3")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort-output.net
index ee6d5fa..94f9896 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort-output.net
@@ -8,30 +8,53 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2:3:4:5:6,s:7:8")
+Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-Layer(1 "top")
+PKG_unknown(unknown,C2,2.2uF)
+PKG_unknown(unknown,R4,2.8K)
+PKG_unknown(unknown,R3,28K)
+PKG_unknown(unknown,R8,1)
+PKG_unknown(unknown,CE2,1pF)
+PKG_unknown(unknown,RE2,100)
+PKG_unknown(unknown,RC1,3.3K)
+PKG_unknown(unknown,Q2,unknown)
+PKG_unknown(unknown,C1,2.2uF)
+PKG_unknown(unknown,A3,.options TEMP=25)
+PKG_unknown(unknown,A2,unknown)
+PKG_unknown(unknown,A1,unknown)
+PKG_none(none,VCC,DC 15V)
+PKG_none(none,Vinput,DC 1.6V AC 10MV SIN(0 1MV 1KHZ))
+PKG_unknown(unknown,CE1,1pF)
+PKG_unknown(unknown,Cout,2.2uF)
+PKG_unknown(unknown,RL,100K)
+PKG_unknown(unknown,RC2,1K)
+PKG_unknown(unknown,RE1,100)
+PKG_unknown(unknown,R2,2K)
+PKG_unknown(unknown,R1,28K)
+PKG_unknown(unknown,R5,10)
+PKG_unknown(unknown,Q1,unknown)
+Layer(1 "component")
(
)
-Layer(2 "ground")
+Layer(2 "solder")
(
)
-Layer(3 "signal2")
+Layer(3 "outline")
(
)
-Layer(4 "signal3")
+Layer(4 "GND")
(
)
Layer(5 "power")
(
)
-Layer(6 "bottom")
+Layer(6 "signal1")
(
)
-Layer(7 "outline")
+Layer(7 "signal2")
(
)
-Layer(8 "spare")
+Layer(8 "signal3")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/cascade-output.net b/gnetlist/tests/common/outputs/gsch2pcb/cascade-output.net
index ee6d5fa..3f5c511 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/cascade-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/cascade-output.net
@@ -8,30 +8,38 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2:3:4:5:6,s:7:8")
+Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-Layer(1 "top")
+PKG_none(none,AMP2,unknown)
+PKG_none(none,T1,unknown)
+PKG_none(none,MX1,unknown)
+PKG_none(none,FL1,unknown)
+PKG_none(none,DEF1,unknown)
+PKG_none(none,AMP1,unknown)
+PKG_none(none,SOURCE,unknown)
+PKG_unknown(unknown,DEFAULTS,unknown)
+Layer(1 "component")
(
)
-Layer(2 "ground")
+Layer(2 "solder")
(
)
-Layer(3 "signal2")
+Layer(3 "outline")
(
)
-Layer(4 "signal3")
+Layer(4 "GND")
(
)
Layer(5 "power")
(
)
-Layer(6 "bottom")
+Layer(6 "signal1")
(
)
-Layer(7 "outline")
+Layer(7 "signal2")
(
)
-Layer(8 "spare")
+Layer(8 "signal3")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/multiequal-output.net b/gnetlist/tests/common/outputs/gsch2pcb/multiequal-output.net
index ee6d5fa..2bdf919 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/multiequal-output.net
@@ -8,30 +8,33 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2:3:4:5:6,s:7:8")
+Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-Layer(1 "top")
+PKG_none(none,V1,DC 1V)
+PKG_unknown(unknown,R1,20)
+PKG_unknown(unknown,A1,abotol=1e-11)
+Layer(1 "component")
(
)
-Layer(2 "ground")
+Layer(2 "solder")
(
)
-Layer(3 "signal2")
+Layer(3 "outline")
(
)
-Layer(4 "signal3")
+Layer(4 "GND")
(
)
Layer(5 "power")
(
)
-Layer(6 "bottom")
+Layer(6 "signal1")
(
)
-Layer(7 "outline")
+Layer(7 "signal2")
(
)
-Layer(8 "spare")
+Layer(8 "signal3")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/netattrib-output.net b/gnetlist/tests/common/outputs/gsch2pcb/netattrib-output.net
index ee6d5fa..c40fb5b 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/netattrib-output.net
@@ -8,30 +8,34 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2:3:4:5:6,s:7:8")
+Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-Layer(1 "top")
+PKG_unknown(unknown,F1,unknown)
+PKG_DIP14(DIP14,U300,unknown)
+PKG_DIP14(DIP14,U200,unknown)
+PKG_DIP14(DIP14,U100,unknown)
+Layer(1 "component")
(
)
-Layer(2 "ground")
+Layer(2 "solder")
(
)
-Layer(3 "signal2")
+Layer(3 "outline")
(
)
-Layer(4 "signal3")
+Layer(4 "GND")
(
)
Layer(5 "power")
(
)
-Layer(6 "bottom")
+Layer(6 "signal1")
(
)
-Layer(7 "outline")
+Layer(7 "signal2")
(
)
-Layer(8 "spare")
+Layer(8 "signal3")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/powersupply-output.net b/gnetlist/tests/common/outputs/gsch2pcb/powersupply-output.net
index ee6d5fa..3804abe 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/powersupply-output.net
@@ -8,30 +8,42 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2:3:4:5:6,s:7:8")
+Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-Layer(1 "top")
+PKG_unknown(unknown,U2,unknown)
+PKG_unknown(unknown,C4,1uf)
+PKG_unknown(unknown,C3,22uF)
+PKG_unknown(unknown,R1,5k)
+PKG_unknown(unknown,C2,0.1uF)
+PKG_unknown(unknown,R2,220)
+PKG_unknown(unknown,C1,2200uF)
+PKG_unknown(unknown,S1,unknown)
+PKG_unknown(unknown,CONN1,unknown)
+PKG_unknown(unknown,T1,unknown)
+PKG_unknown(unknown,F1,unknown)
+PKG_unknown(unknown,U1,unknown)
+Layer(1 "component")
(
)
-Layer(2 "ground")
+Layer(2 "solder")
(
)
-Layer(3 "signal2")
+Layer(3 "outline")
(
)
-Layer(4 "signal3")
+Layer(4 "GND")
(
)
Layer(5 "power")
(
)
-Layer(6 "bottom")
+Layer(6 "signal1")
(
)
-Layer(7 "outline")
+Layer(7 "signal2")
(
)
-Layer(8 "spare")
+Layer(8 "signal3")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/singlenet-output.net b/gnetlist/tests/common/outputs/gsch2pcb/singlenet-output.net
index ee6d5fa..42b0d58 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/singlenet-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/singlenet-output.net
@@ -8,30 +8,31 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2:3:4:5:6,s:7:8")
+Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-Layer(1 "top")
+PKG_DIP14(DIP14,U100,unknown)
+Layer(1 "component")
(
)
-Layer(2 "ground")
+Layer(2 "solder")
(
)
-Layer(3 "signal2")
+Layer(3 "outline")
(
)
-Layer(4 "signal3")
+Layer(4 "GND")
(
)
Layer(5 "power")
(
)
-Layer(6 "bottom")
+Layer(6 "signal1")
(
)
-Layer(7 "outline")
+Layer(7 "signal2")
(
)
-Layer(8 "spare")
+Layer(8 "signal3")
(
)
Layer(9 "silk")
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/stack-torture-output.net b/gnetlist/tests/common/outputs/gsch2pcb/stack-torture-output.net
index ee6d5fa..79a8e98 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/stack-torture-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/stack-torture-output.net
@@ -8,30 +8,31 @@ PolyArea[200000000.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
-Groups("1,c:2:3:4:5:6,s:7:8")
+Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-Layer(1 "top")
+PKG_unknown(unknown,C?,unknown)
+Layer(1 "component")
(
)
-Layer(2 "ground")
+Layer(2 "solder")
(
)
-Layer(3 "signal2")
+Layer(3 "outline")
(
)
-Layer(4 "signal3")
+Layer(4 "GND")
(
)
Layer(5 "power")
(
)
-Layer(6 "bottom")
+Layer(6 "signal1")
(
)
-Layer(7 "outline")
+Layer(7 "signal2")
(
)
-Layer(8 "spare")
+Layer(8 "signal3")
(
)
Layer(9 "silk")
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