gEDA-user: Problem on the rat net in PCB

["Rui Cheang" <ruicheang@hotmail.com>]

Dear,

I found problems on using the pcb, I did create the .sch, .net, and .bom 
files.  They are ok.  When place the componets on the pcb and auto-rat net 
them, it did not succesfull and cause the following Warmings!
...
WARNING! Pin number ending with 'B' encountered in netlist file
Probably a bad netlist file format
Can't find Q1 pin B called for in netlist.
WARNING! Pin number ending with 'C' encountered in netlist file
Probably a bad netlist file format
Can't find Q2 pin C called for in netlist.
WARNING! Pin number ending with 'E' encountered in netlist file
Probably a bad netlist file format
...
something like that and

Both connection alread in netlist - cannot merge nets
Both connection alread in netlist - cannot merge nets
Both connection alread in netlist - cannot merge nets
Both connection alread in netlist - cannot merge nets
Both connection alread in netlist - cannot merge nets
Both connection alread in netlist - cannot merge nets

Here is the .sch, .Bom and .net could u tell me the solutions! Thansk
---sch
v 20021103
C 1900 88500 1 0 0 npn-3.sym
{
T 1800 89400 5 10 1 1 0 0
uref=Q2
T 1600 89200 5 10 1 1 0 0
value=MOD1
T 1900 88500 5 10 0 1 0 0
refdes=Q2
}
C 4100 88500 1 0 1 npn-3.sym
{
T 4000 88700 5 10 1 1 0 0
uref=Q1
T 3800 88500 5 10 1 1 0 0
value=MOD1
T 4100 88500 5 10 0 1 0 0
refdes=Q1
}
C 3100 86600 1 90 0 resistor-1.sym
{
T 3200 87100 5 10 1 1 0 0
uref=RE
T 3200 86900 5 10 1 1 0 0
value=10K
T 3100 86600 5 10 0 1 0 0
refdes=RE
}
N 2500 88500 3500 88500 4
N 3000 88500 3000 87500 4
C 1500 88900 1 0 1 resistor-1.sym
{
T 1100 88700 5 10 1 1 180 2
uref=RS2
T 1000 88500 5 10 1 1 180 2
value=1K
T 1500 88900 5 10 0 1 90 2
refdes=RS2
}
C 2400 90500 1 270 0 resistor-1.sym
{
T 1900 90000 5 10 1 1 0 0
uref=RC2
T 1900 89800 5 10 1 1 0 0
value=10K
T 2400 90500 5 10 0 1 0 0
refdes=RC2
}
C 3400 90500 1 270 0 resistor-1.sym
{
T 3700 90000 5 10 1 1 0 0
uref=RC1
T 3700 89800 5 10 1 1 0 0
value=10K
T 3400 90500 5 10 0 1 0 0
refdes=RC1
}
N 1000 90500 3500 90500 4
{
T 1000 90500 5 10 1 1 0 0
netname=VCC
}
N 3500 89600 3500 89500 4
N 2500 89600 2500 89500 4
C 5200 89100 1 180 0 resistor-1.sym
{
T 4900 89200 5 10 1 1 0 0
value=1K
T 5200 89100 5 10 0 1 0 0
refdes=RS1
T 4500 89200 5 10 1 1 0 0
uref=RS1
}
N 4300 89000 4100 89000 4
N 1000 86600 3000 86600 4
N 5200 89000 5600 89000 4
{
T 5200 89000 5 10 1 1 0 0
netname=VIN
}
N 3300 88100 3000 88100 4
{
T 3300 88100 5 10 1 1 0 0
netname=VOUT
}
C 900 86300 1 0 0 gnd-1.sym
N 1500 89000 1900 89000 4
N 600 89000 200 89000 4
{
T 200 89000 5 10 1 1 0 0
netname=VEE
}


----BOM
package	refdes	device	value
RS1	RS1	RESISTOR	1K
RC1	RC1	RESISTOR	10K
RC2	RC2	RESISTOR	10K
RS2	RS2	RESISTOR	1K
RE	RE	RESISTOR	10K
Q1	Q1	NPN_TRANSISTOR	MOD1
Q2	Q2	NPN_TRANSISTOR	MOD1



--net
VIN	RS1-1
VCC	RC1-1 RC2-1
VEE	RS2-2
GND	RE-1
unnamed_net4	RS1-2 Q1-B
unnamed_net3	RC1-2 Q1-C
unnamed_net2	RS2-1 Q2-B
VOUT	RE-2 Q1-E Q2-E
unnamed_net1	RC2-2 Q2-C



Eu sou Rui, Obrigado!


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