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Re: gEDA-user: HELP with Icarus Verilog, 0.7!
On Wednesday 07 April 2004 05:48 am, Mike Jarabek wrote:
> This situation arises because the various inputs to the LUTs have
> differing Tpd's to the output. The LUT has an `n' bit decoder on it
AHH! This I did not know! Nor was it documented with any of the
resources that I have available to me. I thought the LUT used a regular
(pre-programmed) AND-OR-INVERT matrix to get consistent propegation
delays. I guess manufacturers chose not to do that to minimize
transistors.
Thanks for the heads up.
--
Samuel A. Falvo II